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This is a last ditch effort to try to get an Alliance Memory DDR1 chip (datasheet (http://www.alliancememory.com/pdf/ddr1/128m-as4c8m16d1.pdf)) working with a Cyclone IV FPGA (EP4CE22F17C6) using ALTMEMPHY. The FPGA and RAM are less than 3" apart, traces are length matched, and the design is essentially identical to an Altera reference design. The Alliance RAM doesn't have a memory preset in the megafunction, but I've set all the parameters to be within spec, trying to run at 120 MHz (have also tried 100 MHz). I've gone through all clock phases (0, 90, 180, 270), and 180 looks to match up the best under the scope but still doesn't seem to work. Have tried two chips in case one was a dud. Clock signals cross nicely, no critical warnings in Quartus when compiling. Using normal compilation effort, and standard fit under fitter settings. I've also tried making a smaller program with ONLY a DDR megafunction for debugging.
I am claiming it doesn't work because it fails verification when I try to upload a NiosII elf to it. Also, the local_init_done signal never goes high. I've tried using the Debug GUI program, doing a functional simulation, SignalTap, and looking at it under a scope, but I'm not sure what is preventing it from working. It seems as if it is not coming out of the calibration stage. I've tried to compare the same program with modelsim and under the scope, and I've attached a few pictures. You can see there is a small section at the end which isn't happening on the board that is happening in modelsim, and after that is where the pnf goes high. It finishes it's third rrp_sweep stage and then stops - why? I've also attached the startup sequences for Altera and the memory manufacturer. I'm just kind of out of ideas at this point, if anyone has a hunch, I would be grateful. Thanks http://www.alteraforum.com/forum/attachment.php?attachmentid=9399&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=9400&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=9401&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=9402&stc=1- Tags:
- Cyclone® IV FPGAs
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