Cyclone IV fails to configure below -20C

[Altera_Forum]

I have a Cyclone IV design that operates correctly down to -20C but fails to configure below that temp. I have attached the schematic for the configuration block along with a scope trace showing configuration at room temp. I unfortunately don't have a complete scope trace at cold temp yet, however conf_done never goes high below -20C. If the temperature is ramped up from -40C the device starts working correctly around -20C. Can anyone have a quick look and see if I have botched the configuration set up. This is my 1st experience with Altera devices and I'm at a loss. All devices are rated at -40C or better. 

 Thanks

[Altera_Forum]

Flash memory that you use is EPCS from Altera? What's its operating temperature range?

[Altera_Forum]

--- Quote Start ---  Flash memory that you use is EPCS from Altera? What's its operating temperature range?  --- Quote End ---    Temp range of Altera EPCQ is -40C to +85C, part number EPCQ16SI8N

[Altera_Forum]

I did notice I have the MSEL pins tied to 3.3V instead of 2.5V (VccA). This was copied from another design which does work to below -40C so I don't think that is what is causing my problem.

[Altera_Forum]

Hi murr32, 

 What is the operating temperature range of the CIV device that you are using?

[Altera_Forum]

For commercial part, the Tj is from 0 to 85C. Is your part commercial part? Or with extended Tj -40 to 100/125C?

[Altera_Forum]

All parts are rated to -40C or lower. nCONFIG never gets released by the reset device at temperatures below -20C preventing configuration. This circuit has been used on another project and works down to -45C. It definitely looks like it is not an FPGA problem.

[Altera_Forum]

Does nCONFIG get held low by the FPGA during POR? 

 I have two banks (Banks 2 and 5) powered at 2.5V for a LVDS interfaces and the rest powered at 3.3V for CMOS interfaces, could this be playing havoc with the POR?   Checking the 1.2V core and 2.5V rails now to see if there is a problem with them. We have been able to run several of the boards in house down below -40C and get 100% start-up, the customer's sees problems below -20C. We are using the customer's host in our in house tests and so far have not been able to duplicate the problem. I've run out of straws to grasp at, any more suggestions?

[Altera_Forum]

1.21V and 2.49V at room temp, 1.19V and 2.49V at -40C, so POR shouldn't be a problem.

[Altera_Forum]

Hi murr32, 

 It seems like you have done quite debugging. I think you should file a service request to Altera support on this.

[Altera_Forum]

--- Quote Start ---  I did notice I have the MSEL pins tied to 3.3V instead of 2.5V (VccA). This was copied from another design which does work to below -40C so I don't think that is what is causing my problem.  --- Quote End ---  This shouldn't be a problem, as long as the 3.3V supply comes early at power up, or at least not too much later than the 2.5V. AFAIK the MSEL pins are sampled very early in the startup process, just after the 2.5V and 1.2V supplies have come, and the pins need to have the required voltage at that time. Can you put a scope on the EPCQ lines? That way you can find out whether the FPGA is trying to read from the flash or not (which will rule out a bad reading of the MSEL pins... or confirm it). And you can check also whether the quality of the signals themselves, you could have some glitches or bouncing on the clock that gets worse at low temperatures.

[Altera_Forum]

The reset controller looks like the culprit to me, or the 3.3V rail (which you didn't measure above). Just to isolate the problem, can you lift a lead on the reset controller so it can't pull nCONFIG low, then configure the part via JTAG in the failing temperature range? 

 One other thing to note is that you've got the MSEL pins set for the fast POR delay. According to the CIV handbook: "The fast POR time option has stricter power-up requirements when compared with the standard POR time option." This could be something to look at, but it would not cause the reset controller to keep pulling nCONFIG low. That still points to the reset controller.

[Altera_Forum]

--- Quote Start ---  The reset controller looks like the culprit to me, or the 3.3V rail (which you didn't measure above). Just to isolate the problem, can you lift a lead on the reset controller so it can't pull nCONFIG low, then configure the part via JTAG in the failing temperature range?  One other thing to note is that you've got the MSEL pins set for the fast POR delay. According to the CIV handbook: "The fast POR time option has stricter power-up requirements when compared with the standard POR time option." This could be something to look at, but it would not cause the reset controller to keep pulling nCONFIG low. That still points to the reset controller.  --- Quote End ---    Yeah, that's what we have found also. It turns out the tolerance on 3.3V, the tolerance of the reset controller, and the hysteresis of the controller combined to make it marginal at -40C. We have replaced the reset controller with a lower threshold version and all is good.  Thanks everyone for time and suggestions.

[Altera_Forum]

Thanks for sharing on the finding and resolution.

[Altera_Forum]

Hi murr32, 

 Thanks lot for sharing the root cause and fix.