Cyclone V 2.5V LVPECL vs LVDS inputs

[TonyK]

When feeding an AC coupled LVPECL differential signal into a Cyclone V FPGA, the Cyclone V datasheet appears to indicate that DC bias and OCT 100 ohm differential termination is not available when Assignment editor specifies differential I/O as LVPECL.  Furthermore, LVPECL inputs are limited to CLK input pins.

Questions:

1.  Are my comments above correct?

2.  Per Cyclone V datasheet LVDS I/Os appear to be able to receive an AC coupled LVPECL signal which would enable internal chip provided DC biasing and OCT 100 ohms by simple Assigning LVPECL input to LVDS in Assignment editor.  Is this true?  Are there any negatives?

Thank you in advance,

Tony

[EthanLi]

Hi,

This is Ethan from Intel AE team.

LVPECL inputs are limited to CLK input pins.

Do you use the transceiver pin or GPIO pin? If it is a GPIO pin, there is no internal AC/DC coupling.

If it is a transceiver  pin, you can turn on the OCT option in the assignment.

For the assignment , you can refer to the KDB below.

https://www.intel.com/content/www/us/en/support/programmable/articles/000083679.html 

You need to specify LVDS in Quartus since if you specify LVPECL the fitter will error if Rd is turned on.  The reason why we don’t support Rd with LVPECL is the larger common mode range – our Rd doesn’t meet its tolerance specs at the expanded LVPECL range compared to LVDS. The termination does not meet all the specs at the expanded LVPECL range to LVDS.

So please make sure  LVPECL vocm and vod meets our LVDS receiver’s specs. 

Thanks,

Ethan

[FvM]

Hi,
what are you trying to achieve? It's always possible to interface other differential IO standards to LVDS input, probably with the help of external hardware, e.g. termination resistors and passive level shifters.

[TonyK]

My goal is to limit external components of the AC coupled differential LVPECL input signal to the GPIO pins.  If I assign input as LVPECL I am limited to CLK input pins, and no on chip termination is provided or DC biasing for my AC coupled LVPECL signal.  Datasheet does not appear to indicate Vid other than recommend when <700Mbp Vid for optimum performance: 0V to 1.85V (>700Mbps Vid 1V to 1.6V).  In my application the signal is 160Mbps.  By selecting LVDS input the LVPECL signal will receive the benefit of on chip 100 ohm termination and chip provided DC bias.

Thank you for your feedback,

Tony