Cyclone V (5CGTFD9) 4X PCIe Connections for Data Lines and RefClk

[ToddW]

I need some guidance on properly connecting PCIe interface to the XCVR banks on a Cyclone V D9 (12 XCVR channels) to get PCIe Gen2 X4 (5Gbps) signaling to work correctly.  I copied the C5 DVK layout, but am only getting 2.5 Gbps rates and only 1-2X lanes are connecting.

The C5 datasheet (cv_5v3-683586-670578) for XCVRs for this device in Figure 1-5 describes the XCVR configuration for our Cyclone V chip (a GT device with 12 XCVR channels). It says that Ch1-2 in both GXB_L0 and GXB_L2 are the "PCIe Hard IP" regions.  However, the C5 DVK schematic (which I copied for our design), shows the PCIe signals connected to GXB_L0/L1 Channels 0-3. Channels 0 and 3 are not part of the PCIe Hard IP.  Consequently, there appears to be a conflict between how the DVK PCIe lines are connected vs the recommended connection guidelines from the datasheet.  Please clarify the proper connections to realize a PCIe 4X Gen2 (5Gbps).  

Another question that I have is what is the best reference clock input to enable our 4X 5Gbps configuration?  The C5 DVK has the PCIe RefClk pair coming into REFCLK1L (pins W11/V10).  Should this be connected to REFCLK0L (pins AA11/AB10)?

The "Configuration via Protocol (CvP) datasheet (ug_cvp-683889-666868) states in Notes 2 & 3 of Figure 1-1:

2. PCIe Hard IP block (bottom left) for CvP and other PCIe applications.
3. PCIe Hard IP block only for PCIe applications and cannot be used for CvP.

[ToddW]

[ventt]

Hi @ToddW,

Thanks for reaching out.

Allow me some time to investigate your issue. I shall come back to you with the findings.

Thanks.

Best Regards,

Ven

[ventt]

Hi @ToddW,

Are you referring to the Cyclone V GT dev kit?

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html

According to Figure 1-5 in Cyclone V Device Handbook Volume 2: Transceivers (ug-cv_5v3-683586-670578), the PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2. This means the PCIe Hard IP block is located near the mentioned channels. It does not mean that the PCIe Hard IP cannot use channels such as 0 and 3. 

Please connect the input reference clock to pin W11 (PCIE_REFCLK_P) and V10 (PCIE_REFCLK_N). Ensure that the DIP switches on the dev kit are set to default positions following Section 4.2: https://www.intel.com/content/www/us/en/docs/programmable/792833/current/factory-default-switch-and-jumper-settings.html

You may try the Cyclone V PCIe Gen 2.0 x4 design from the FPGA Design Store and refer to the QSF for the pin assignments of PCIe signals. It works for the Cyclone® V GT FPGA Development Kit DK-DEV-5CGTD9N to bring up the Gen2 x4 configuration:

https://www.intel.com/content/www/us/en/design-example/749022/cyclone-v-fpga-pcie-2-0-x4-avalon-memory-mapped-dma-design-example.html

Thanks.

Best Regards,

Ven

[ventt]

Hi @ToddW,

May I know if you have further questions on this forum?

Thanks.

Best Regards,

Ven

[ventt]

Hi @ToddW,

As there are no further inquiries, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

Ven