Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21598 Discussions

Cyclone V A7 problem downloading ELF to Nios in SBT

Altera_Forum
Honored Contributor II
1,924 Views

I have a 5CEFA7F31C6N design. I have it built and complied in Quartus and can load the SOF with a USB Blaster from either the Quartus programmer or from inside SBT Eclipse tools.. but I cannot get the ELF to load into the Nios. I have tried this on two boards and they both behave exactly the same. 

 

I get the following error message when I try to load from inside SBT using "run as configuration" ... 

 

using cable "usb-blaster [usb-0]", device 1, instance 0x00 

resetting and pausing target processor: failed 

leaving target processor paused 

 

I have confirmed that conf_done is high (sof loaded), the core clock is present, the logical reset is high.... I notice that when I bring up the "create, manage, and run configurations" window with the "Target Connection" tab selected inside "Run Configurations" that the Processor name is not correct and the Byte Stream Device name is not correct either. 

 

I've also tried to load the flash directly through the Nios Command Shell but it has the same problem.. it cannot get the NIOS to cooperate.. It looks to me like either the Nios is not running or their is a mismatch in the actual names and expected names and that is causing the system to break down. 

 

The actual names are viper_nios for the processor and jtag_uart_0 for the stream device but the SBT Run shows them as nios2_0 & jtaguart_0 inside the window that I listed above... It will still "seem" to get a connection after trying a few times but when I hit run it chokes and throws up the error that I listed above. I've done a lot of other things to try and get around this but I'm hoping that somebody will have an idea or be able to point me in a new direction...  

 

Any ideas? 

 

david coburn
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
470 Views

First of all. ¿do you add the system ID component in the SOPC Builder or Qsys Editor? When you add a nios processor you have to check the "cpu id" option. You can locate it in some folder of nios ii component. In my experience you can't get a good communication between nios system and the eclipse ide, if you don't check this option. 

 

Don't forget, in the nios eds ide, to regenerate the bsp for your system, and the try to download the elf file. ( Ignore the timestamp mismatch during communication ).
0 Kudos
Altera_Forum
Honored Contributor II
470 Views

bertulus, 

 

thank you for the reply... 

 

1) yes, I have a System ID Peripheral in set to 0x00012345.  

note: when I am in SBT and in the Run As Configuration window I can see that the tool knows that it is supposed to be 0x00012345 but it cannot confirm that number with the hardware... again, Nios isn't talking back for some reason. 

 

2) yes, I also have the cpu id checkbox clicked and the value is 0x00000001. I played with this a bit and when I would uncheck it a message would appear that said "Info: nios2_0: CPUID control register value is 0. Please manually assign CPUID if creating multiple Nios II system"... I do not have mulitple NIOS's in this design but I went ahead and checked it and assigned it to 0x00000001. 

 

I have also gone back and removed everything from the Qsys project except the following: 

1) Clock Source being fed by an external ckt at 50Mhz. 

a) The output clock and resets drive all the following IP blocks 

 

2) Nios II/f  

a) reset vector at 0x1800  

b) exception vector at 0x100020 

c) cpuid at 0x00000001 

d) JTAG Debug port level 1 break vector at 0x820 (this is from inside the wizard) 

e) jtag_debug_module address 0x800 (this is from the base address column in the Qsys "System Contents" view ... I think this is fine and the differences between the values of d & e are simply due to the offset of 0x20 

 

3) System ID Peripheral at 0xa000 

 

4) On-Chip Memory RAM 

a) address of 0x100000 

b) 32 bit bus 

c) 64kbytes total 

d) Slave s1 Latency of 1 

 

5) JTAG uart at 0x10c0  

 

6) EPCS/EPCQx1 Serial Flash Controller at 0x1800 

 

Do you see any problems with the above settings? I believe that this is going to turn out to be some tool vs. Cyclone V problem, but I'm not sure... Also, I have multiple boards and I've tried two and they both exhibit the same issue.. No problem downloading SOF but cannot load the ELF 

 

thanks, 

david
0 Kudos
Altera_Forum
Honored Contributor II
470 Views

I'm doing my first steps with nios. With SOPC Builder and Nios EDS I have good results. I try to do the same with Qsys but I can't connect with Nios. 

 

You add a EPCS controller. In a nios system I made with a bootloader, i can't run the firmware via jtag from the nios ide. The only thing I could do with success was download fpga configuration via jtag, and the the configuration+bootloader+firmware image to the epss memory. I cycle the power and works. 

 

The only idea I have in mind is delete some components like epcs controller, jtag uart so the system become the smallest. If it works, try to add the components deleted, one at a time so you can see who is presenting troubles.
0 Kudos
Altera_Forum
Honored Contributor II
470 Views

bertulus, 

 

I have been using Qsys for quite some time now and have had no problems with it and Nios... I believe that my problem revolves more around my part being a Cyclone V more than anything else, but I am not sure...  

 

In your message when you say that you cannot run the firmware via jtag from the nios ide --> what part are you using in this situation? 

 

thank you, 

david
0 Kudos
Altera_Forum
Honored Contributor II
470 Views

I try with the Altera DE1 Board ( EP2C20F484 ) and with a custom board I made with EP2C5T144C8.

0 Kudos
Reply