Cyclone V + ALTLVDS + Multi-channel ADC

[Altera_Forum]

Dear all, 

I am trying to fit a design in a Cyclone V FPGA (E series, A7, FBGA 484 pins). The FPGA receives 16 LVDS channels at 875 Mbps each. The data comes from a LTM9011-14 ADC from Linear Technology. The ADC outputs the data with a fast clock at 437,5 MHz, center aligned with the data, and a slow clock at 62,5 MHz, edge aligned with the data.  I am diving in the documentation but I cannot clear my mind.  What is the best configuration to use with ALTLVDS_RX? how do I constrain the design so as to make quartus understand that the fast clock is center aligned, while the slow clock is edge aligned? external or embedded PLL? if external, what compensation mode should I use? how do I use both fast and slow clock inputs?  Thank you for your help in advance, Giancarlo

[Altera_Forum]

Did you request the reference design from Linear Tech? They have the ref design, however, which base on Xilinx devices.

[Altera_Forum]

According to Cyclone V datasheet, -7 speedgrade doesn't handle 875 MBPS. It's the maximum achievable bitrate with -6 speedgrade. 

 Operating the serial receiver near the speed limit suggests to use a PLL dynamic phase shift feature and implemenent an automatical clock phase adjustment.  I haven't yet implement serial ADC interfaces with Cyclone V, thus I can't help you with the device related details. With Cyclone III and IV, that only have software SERDES, I found it more convenient to build my own SERDES block based on DDIO and PLL function, because the ALTLVDS_RX implementation has several restrictions.

[Altera_Forum]

What's your ADC's sampling frequency? 

 I assume your speed is 100Mhz, and ADC's resolution is 14-bit. So your data rate will be 1400Mbps. LTM9011 support 2-Lane ouput mode, which means the maximum data speed can be decreased to 700Mbps. AS FvM said, only -6 grade device can support 875 Mbps. But i don't if -7 grade deivces can support above 700Mbps. You must check datasheet to confirm.

[Altera_Forum]

Also, when you using 2-lane mode, it mean you need more lvds pins. You said that you used 16 pair lvds in you first post. So i think you want to use one Cyclone V FPGA device to process 2 LTM9011 (each has 8 channels). So if you use 2-lane mode, you need prepare 32 pairs lvds pin.  

 Another question is that you need at least 4 lvds module, if you use altera's lvds module to receiver these two ADCs data. So the question can four lvds modules be implemented inside one FPGA. Otherwise, you need to design the lvds receiver using user logic instead of Altera's lvds megafunction.

[Altera_Forum]

The parameters in the initial post makes sense if Giancarlo wants to use 2-lane 14-bit mode at 125 MSPS.