Cyclone V DDR3 controller driver

[Altera_Forum]

Hi, 

 I'm attempting to interface with external DDR3 memory on the Cyclone V GX development board. I want to control writing to and reading from the memory with a custom block. I do not want to involve the NIOS or a DMA. As for using the megawizard or Qsys components I don't have a preference.   I have an avalon stream of data that I want to save to DDR3. As I understand it I will have to convert this stream to an Avalon Memory Mapped interface to use it with the memory controller. Aside from that I have been having trouble learning how to interface with the Memory Controller. How to write and read etc. My only previous experience is with internal M10K memories, I am a total beginner with external memories.   Ideally I would love to find a VHDL example of writing something to the DDR3 memory controller with a custom block.   So far I have tried to follow Qsys tutorials, the example megafunction project and several other documents (External memory handbook etc). But I am still struggling.   If anyone has any examples of interfacing to the DDR3 memory controller with a custom block or any other advice or where to look it would be much appreciated.   Thanks

[Altera_Forum]

Hi 

 I am having similar problems. Why does the MegaWizard generate a Verilog example design, when I have chosen VHDL?

[Altera_Forum]

I also need the timing diagram of the custom block to control the HMC.