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Altera_Forum
Honored Contributor I
827 Views

Cyclone V E Development Board Kit

Hi all,  

I have Cyclone V E Development board kit. In the user guide, it said the frequency could go up to 810 MHZ by using Clock Control Application. But in the Cyclone V datasheet, it said "Global clock and Regional clock" is just go up to 460MHz and Max of "Output frequency for internal global or regional clock" for PLL is 460 MHz. How is Clock Control application get 810 MHz for clock input of programmable si570 oscillator?  

 

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6 Replies
Altera_Forum
Honored Contributor I
51 Views

Let me clarify this: 

 

1. The Cyclone V E dev Kit has an external on-board programmable oscillator Si570 whose frequency range is 10Mhz to 810MHz. This means that you can use this Si570 oscillator to generate any frequency between this range. You could use this as an input to the FPGA also.  

 

2. The Cyclone V Series FPGA thats on the board has 4 PLLs, whose max frequency is 560-660MHz. This means that these PLLs, depending on the exact device, can generate clocks with a maximum frequency of 550-650MHz. The core logic in the FPGA may be optimized for these operating frequency ranges to ensure you do not have any clock jitter/routing issues as well as timing issues.
Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

Let me clarify this: 

 

1. The Cyclone V E dev Kit has an external on-board programmable oscillator Si570 whose frequency range is 10Mhz to 810MHz. This means that you can use this Si570 oscillator to generate any frequency between this range. You could use this as an input to the FPGA also.  

 

2. The Cyclone V Series FPGA thats on the board has 4 PLLs, whose max frequency is 560-660MHz. This means that these PLLs, depending on the exact device, can generate clocks with a maximum frequency of 550-650MHz. The core logic in the FPGA may be optimized for these operating frequency ranges to ensure you do not have any clock jitter/routing issues as well as timing issues. 

--- Quote End ---  

 

 

Thank you so much for your info. How about's clock network? Global Clock Network and Regional Clock Network? What are they used for? In the Cyclone V Data sheet, it shows that their max is 460Mhz. It makes me confusing with programmable si570 oscillator.
Altera_Forum
Honored Contributor I
51 Views

The Global Clock Networks are used to route the Clock signals to various parts in the FPGA. These are specialized clock tree networks that have low Jitter and delay. This means that they can route clocks with a max frequency of 460MHz. This will be the same as that of the Max output frequency fmax-out of the PLL. Clock Tree networks are optimized for those particular frequency ranges. Running clocks more than this rated freq may produce unwanted glitches or jitters.

Altera_Forum
Honored Contributor I
51 Views

 

--- Quote Start ---  

The Global Clock Networks are used to route the Clock signals to various parts in the FPGA.  

--- Quote End ---  

 

 

Could you tell me more about "various parts"? More specifically. If you could provide a example it would be great.
Altera_Forum
Honored Contributor I
51 Views

Well, FPGAs have the following blocks in them, depending on the type and family of FPGA: 

 

1. IO Pins 

2. IO Blocks 

3. LUTs - Look up tables 

4. LE - Logic Elements/ Logic Blocks 

5. SRAM/MRAM blocks - M9K,M20K,etc 

6. PLLs 

7. Embedded processor Cores - ARM Cortex M9 (depends on FPGA family, not all FPGAs have them)
Altera_Forum
Honored Contributor I
51 Views

It's great example. Thank for your information.

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