Cyclone V GT Native PHY for 5Gbps USB 3.0?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cyclone V GT Native PHY for 5Gbps USB 3.0?

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Hi,

I need assistance with properly configuring a Cyclone V GT transceiver in Native PHY mode such that it can capture USB 3.0 / 5 Gbps data. I have a prototype setup with a HSMC card attached to a Cyclone V GT Development Kit. The HSMC board sends copies of upstream as well as downstream USB 3.0 data to the FPGA. The current test design (at below link) shows that the Transceiver incorrectly detects USB 3.0 LFPS as "locked to data" and starts receiving garbage. Please see stp2.stp for powerup trigger (reset sequence) and normal trigger (locked to data [false]).

Could you please give some ideas how to properly configure the Native PHY to capture 5 Gbps USB 3.0 data? This is for a USB 3.0 protocol analyzer so only the RX path is used.

Thank you.

http://www.summitsoftconsulting.com/temp/cyclonev_gt_devkit_test2.qar

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