Cyclone V GT PCIe link

[Altera_Forum]

Hello, I am trying to set up a Cyclone V GT Development Board in a PCIe slot of a desktop running Ubuntu 16.04 

 Essentially, what I would ideally have is the board in the PCIe port of the Linux desktop such that I can update the core image through the PCIe link. As far as I understand it, this can be achieved by uploading a periphery image (a .periph.jic file) to the board and then any core image that has a compatible pin layout can be uploaded through the PCIe link.   I do not have any cable that can connect to the 10 pin header on the board, so I wanted to ask how necessary the cable is. I believe it is required in order to do any programming in Active Serial mode, but not for JTAG. I have been trying to program the EPCQ256 chip on the board indirectly through JTAG (USB Blaster II on the USB port) by using the factory SFL image on the Cyclone V as a bridge. However, I have not been able to successfully do this. I keep receiving a “Can’t recognize silicon ID” error in Programmer that leads me to believe I have made a faulty assumption about how the SFL image is supposed to allow the periphery image to be programmed.   I have been following the tutorial (Beginning on page 33) in section 5-4 of https://www.altera.com/en_us/pdfs/literature/ug/ug_cvp.pdf as much as I can, but it is meant for a Stratix FPGA instead, so I would like confirmation that these steps are still valid (assuming I change the device to match mine).   I am using the Avalon Stream PCIe g1x1 project in this download link: https://www.altera.com/content/dam/altera-www/global/en_us/others/support/refdesigns/ip/interface/pcie_cvgt_avst_on_chip_mem_150.zip    I can split the generated .sof file successfully and I can program the .sof file itself successfully such that the FPGA will appear on a lspci after a soft reboot.   I know the MSEL pins are important for setting the programming mode and I am aware that the MAX V chip needs to have the image provided at https://www.altera.com/support/support-resources/knowledge-base/solutions/rd02112014_88.html in order for the EPCQ256 to load the image properly once it has the .periph.jic image.     I appreciate any help that you can provide and anything that you can confirm I am doing correctly/incorrectly. Please let me know if there is more information that you need.   Best regards, Alex

[Alexander_M_Intel]

I posted the relevant information for answering my post where this link leads to:

https://forums.intel.com/s/question/0D50P000040YDFZSA4/note-on-cvp-tutorial-for-vseries-linux

[LinuxFanatic2018]

You must create your custom board where FPGA programmed by some microcontroller in your favorite mode. Once you have such startup​ system, you will be able to change firmware inside flash IC through same microcontroller and PCIe link. Of course all this is not so easy, but if you have serious plans of updating firmware in such a way then dev board is not enough for you I think.