I have a cyclone V GX on a custom board on which the PLLs do not consistently lock on to the reference clock. The board is based on the terasic Cyclone V GX development board and has the same SiLabs 5338 external PLL generating 125Mhz and 50Mhz along with a 50Mhz oscillator fed into the FPGA through a clock buffer. This provides 4 50Mhz reference clocks and 1 125Mhz reference clock. When I try to generate 2 100Mhz clocks from 2 separate PLLs fed by a 50Mhz and the 125Mhz one PLL will lock and the other will not. When I load the same design into 2 different boards I get inconsistent results, on one board the 125Mhz derived PLL will lock and the 50Mhz will not. While on the other board the 50Mhz derived PLL will lock and the 125Mhz will not. If I change which 50Mhz oscillator is fed to the 50Mhz PLL the results also change with a working 125Mhz sometimes failing to lock and the 50Mhz becoming functional. I have examined the clocks with an oscilloscope and the signal is clean and there is little jitter. I have also looked that the FPLL power supply and there is only 10mVpp-20mVpp ripple. The compile to compile variation seems to be due to which physical PLL quartus assigns, but I can't find anything which would cause the board to board variation. Any suggestions for how to debug or what the issue might be would be very appreciated.
Further debugging has shown that on one board of the 6 physical PLL blocks shown in the chip planner. When 6 PLLs are instantiated from the same clock source the same 2 physical PLLs will lock on and oscillate no matter what clock source is used. Of the remaining 4, 2 will oscillate but not assert the locked signal, and 2 will be stuck high or low with no lock signal.FRACTIONALPLL_X0_Y54_N0 locks and oscillates FRACTIONALPLL_X0_Y30_N0 oscillates FRACTIONALPLL_X0_Y14_N0 stuck high or low FRACTIONALPLL_X0_Y1_N0 locks and oscillates FRACTIONALPLL_X68_Y1_N0 oscillates FRACTIONALPLL_X68_Y54_N0 stuck high or low
Multiple PLLs running at or near the same frequency can "talk" to each other and cause problems. This may be a situation where you have to manually change PLL settings to vary the VCO frequencies between the PLLs. Here's is one mention about this issue from Altera:https://www.altera.com/support/support-resources/knowledge-base/solutions/rd03282014_193.html This does not apply to Cyclone V, but I think the principles always apply. You may have to rethink you clocking architecture to get around this. I would open a service request with Altera and see if they have any restrictions or guidelines that you're not aware of.
Thanks for the reply, I wasn't aware that could be an issue. In the end I only need one PLL to function for the design, I just tested all of them at once to see which ones would lock and which wouldn't. I did a series or tests where I only instantiated one PLL and assigned it to each physical PLL in turn. The results matched the 6PLL test with X0_Y54 and X0_Y1 working properly and the rest not. Unfortunately when tested across 3 boards there isn't one PLL with locks on all three, that would at least allow things to push forward.
eventually found my problem, I went through the pin config document again and realized we accidentally left the RREF_TL pin unconnected. The document states it needs to be connected through a 2K 1% resistor to ground, and the Terasic reference design includes it. Luckily it is on an edge ball so I was able to rework in a piece of magnet wire and connect the resistor. Once I did all of the PLLs in my test case started running and locking properly.