Cyclone V HPS UART, can't rx data

[Altera_Forum]

I can send RS232 data via HPS UART1 but unable to read data. The scope shows RS232 data on RX pin but test code can’t read any data from /dev/ttyS1 and nothing when I ‘cat /dev/ttyS1’ 

 I can think of multiple reasons but right now I’m double checking the FPGA implementation. The RS232 pins that are used for UART1 are different then default. This has been implemented opening QSYS and select the HPS system, then select ‘peripheral pins'. Scroll down to the UART Controllers. Set the UART1 to use the FPGA fabric for it’s pinout. After generating the HDL the uart pins show up for connection, these are brought up to top.vhd and connected to the correct signals. The correct pins and voltages levels are called out in top.qsf. Please see attached photos  One question I regarding FPGA implementation: In QSYS should HPS pin mode be set to ‘FPGA’ or should be set to ‘HPS I/O set’ and then use LoanIO to map to different pins?

[Altera_Forum]

--- Quote Start ---  I can send RS232 data via HPS UART1 but unable to read data. The scope shows RS232 data on RX pin but test code can’t read any data from /dev/ttyS1 and nothing when I ‘cat /dev/ttyS1’  I can think of multiple reasons but right now I’m double checking the FPGA implementation. The RS232 pins that are used for UART1 are different then default. This has been implemented opening QSYS and select the HPS system, then select ‘peripheral pins'. Scroll down to the UART Controllers. Set the UART1 to use the FPGA fabric for it’s pinout. After generating the HDL the uart pins show up for connection, these are brought up to top.vhd and connected to the correct signals. The correct pins and voltages levels are called out in top.qsf. Please see attached photos  One question I regarding FPGA implementation: In QSYS should HPS pin mode be set to ‘FPGA’ or should be set to ‘HPS I/O set’ and then use LoanIO to map to different pins?  --- Quote End ---    So for the HPS to use it, it should be set to "HPS I/O Set" something, for the FPGA then you set it to Loan I/O if using a controller in the FPGA, otherwise the UART itself will go to the FPGA. Really depends what you're trying to do here. Can you post clearer pictures? I'm not sure where you're trying to run pins to and from.

[Altera_Forum]

Thanks for the reply. Trying to communicate from external RS232 device to Cyclone through HPS Linux application software. Problem is the RS232 pins that are wired to Cyclone are different from the default UART1_TX, UART1_RX pins that come up when you click "HPS I/O Set 0".  

 I can draw up a block diagram of pins/connections if you'd like to dig in more. Also if routing to pins that aren't the default HPS I/O pins isn't a possibility can look into different solution.

[Altera_Forum]

--- Quote Start ---  Thanks for the reply. Trying to communicate from external RS232 device to Cyclone through HPS Linux application software. Problem is the RS232 pins that are wired to Cyclone are different from the default UART1_TX, UART1_RX pins that come up when you click "HPS I/O Set 0".   I can draw up a block diagram of pins/connections if you'd like to dig in more. Also if routing to pins that aren't the default HPS I/O pins isn't a possibility can look into different solution.  --- Quote End ---    Any luck yet? I'd recommend drawing up something quick and just posting it if you're still seeing issues. To me, it sounds like an FPGA pin setting is wrong (ie input/output/voltage level)

[Altera_Forum]

I was able to get working by declaring '1' on input pins CTS, DSR, DCD, RI and by generating and updating preloader/uboot.

[Altera_Forum]

--- Quote Start ---  I was able to get working by declaring '1' on input pins CTS, DSR, DCD, RI and by generating and updating preloader/uboot.  --- Quote End ---     You know what, that actually makes some sense to. Great to hear!

[Altera_Forum]

Hi, 

 I am encountering the same issue. I've tried to do the following "declaring '1' on input pins CTS, DSR, DCD, RI" hps_ips_hps_0# (  .F2S_Width (2),  .S2F_Width (2)  ) hps_0 (  .h2f_mpu_eventi (), // h2f_mpu_events.eventi  .h2f_mpu_evento (), // .evento  .h2f_mpu_standbywfe (), // .standbywfe  .h2f_mpu_standbywfi (), // .standbywfi  .uart1_cts (1'b1), // uart1.cts  .uart1_dsr (1'b1), // .dsr  .uart1_dcd (1'b1), // .dcd  .uart1_ri (1'b1), // .ri   .uart1_dtr (hps_0_uart1_dtr), // .dtr  .uart1_rts (hps_0_uart1_rts), // .rts  .uart1_out1_n (hps_0_uart1_out1_n), // .out1_n  .uart1_out2_n (hps_0_uart1_out2_n), // .out2_n  .uart1_rxd (hps_0_uart1_rxd), // .rxd  .uart1_txd (hps_0_uart1_txd), // .txd  But it changes nothing. I use original u-boot and kernel 4.8. And I am wondering if the following "generating and updating preloader/uboot." maybe matters in this case. If it does what should be changed at u-boot before generation it?  Btw, I got something like this while running minicom on /dev/ttyS1 (with and without pins routing to FPGA enabled) [ 23.302445] ttyS1 - failed to request DMA  What could go wrong? Thanks in advance

[Altera_Forum]

Preloader and U-boot updates are important to set pin settings of Cyclone V. Don't expect it to work without it

[Altera_Forum]

Thanks. 

Could you please point or share with me any documentation about this? Or maybe which part of preloader needs to be changed? I've read a few paperas about routing pins from hps to fpga but none of them mentioned about any changes at preloader.

[Altera_Forum]

https://rocketboards.org/foswiki/view/documentation/gsrd140preloader 

 https://www.google.com/search?q=cyclone+v+generate+preloader&oq=cy&aqs=chrome.0.69i59j69i57j0l2j69i61l2.1867j0j4&client=ms-android-verizon&sourceid=chrome-mobile&ie=utf-8#xxri=2    --- Quote Start ---  Thanks. Could you please point or share with me any documentation about this? Or maybe which part of preloader needs to be changed? I've read a few paperas about routing pins from hps to fpga but none of them mentioned about any changes at preloader.  --- Quote End ---                       

[Altera_Forum]

Thanks a lot

[Altera_Forum]

One more question. 

I build preloader (SPL) from u-boot sources (https://github.com/altera-opensource/u-boot-socfpga, socfpga_v2013.01.01) with handsoff defaults from repository:  make mrproper  make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- socfpga_cyclone5_config  make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-  I get u-boot.img and u-boot-spl.bin. The last one I use to build preloader-mkpimage.bin:  mkpimage --header-version 0 -o preloader-mkpimage.bin u-boot-spl.bin u-boot-spl.bin u-boot-spl.bin u-boot-s pl.bin  But after updating SD card's partition 2 with this .bin (dd if=preloader-mkpimage.bin of=/dev/mmcblk0p3 bs=64k seek=0) - board doesn't boot at all.  And now I am wondering if there is anything which I should modify (at prloader/u-boot sources) before building u-boot-spl.bin.  u-boot build with the same way (u-boot.img) works fine.  I've tried to build preloader-mkpimage.bin according to the https://rocketboards.org/foswiki/view/documentation/avgsrdpreloader as well but results are the same - board doesn't boot at all - no single character on serial console.   Thanks

[Altera_Forum]

Hi, 

 I am trying to establish an UART communication between two cyclone V SoCs. I am using the FPGA option enabled in Qsys for UART in both SoCs. I have got the communication running between them, for eg. I can send a string using 'echo hello SoC > /dev/ttyS1' and my application running on other SoC receives the string. Now I am running an application at Tx side, where I want to send a string(for test purposes, later on will be a data of around 20 bytes) cyclically,(running Angstrom with a RT patch). However, at the Rx side, I receive the string only once, and then the 'read' function call blocks. At the Tx side, the further transmission fails with an error 'Invalid Argument', basically for the 'write' function. However, the first write succeeds. Here is a snippet :    // Init code, common for both SoCs.    if ((file_des_uart = open("/dev/ttyS1", O_RDWR | O_NOCTTY )) < 0) { perror("Failed to open the UART device file: "); exit(1); } else { puts ("uart ok"); } struct termios options; tcgetattr(file_des_uart, &options); options.c_cflag = B115200 | CS8 | CLOCAL | CREAD; //<Set baud rate options.c_iflag = IGNPAR; options.c_oflag = 0; options.c_lflag = 0; tcflush(file_des_uart, TCIFLUSH); tcsetattr(file_des_uart, TCSANOW, &options);   //At Tx side   char* tx_buf = "Hello SoC"; while(1 && cntr < 5) { bytesSent = write(file_des_uart,(tx_buf),(strlen(tx_buf)+1)); if(bytesSent != strlen(tx_buf)+1) { perror("Error: "); break; } cntr++; //break after sending 5 times   // At Rx side   while(1) { if ((bytesSent = read(file_des_uart,(void*)rx_buf,50)) > 0) { printf("uart : Received msg = %s\n",rx_buf); } if(bytesSent < 0) { perror("uart : error in reading uart : "); //break; } if(bytesSent == 0 { printf("No data"); } }   As far as I know, I am not using the DMA option, since I have not configured it anywhere, and I prefer not to use it. I would like to have a simple UART communication, between the two SoCs.   Does anyone have a hand on this issue?