Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18988 Discussions

Cyclone V Hard Memory Controller MPFE bandwidth

Honored Contributor II

I have a QSYS design which uses DDR memory. The DDR memory is clocked at 400Mhz in the Hard Memory Controller, and is 32 bits wide, so max bandwidth (not allowing any latency!) is 2*400,000,000*32 = 25.6Gbps. 

I then connect the Multi-Port Front-End (MPFE) controller of the HMC up by setting 2 ports, both 128 bits wide, bidirectional. There are clocked at 168MHz, so theoretical bandwidth on each of these is 128bits * 168MHz = 21.5Gbps. 


I now have some VIP suite Frame Buffers hooked up and I run into bandwidth problems. I start with 1 frame buffer enabled, processing 1080p60 video, which is 1920x1080x20 (bits per pixel) x 60 (frames per second) = 2.5Gbps. The Frame buffer has a read and a write port, so we actually need 5Gbps. Running 1 frame buffer at 1080p60 is fine. If I enable a second one though, they both struggle for bandwidth (it seems) as the video breaks up. Given that we're at 2/5 bandwidth of the DDR memory itself, and around 1/2 bandwidth of one AVL interface to the MPFE we should be fine. I have another design that this works fine with, but I cannot get it to work in this one. 


If anyone could check my bandwidth calcs, and/or explain why I would be limited in my bandwidth then I'd greatly appreciate it. 



0 Kudos
0 Replies