Cyclone V: PCIe x4 + XAUI.

[Altera_Forum]

Hello! 

 I have 5CSXFC6D6F31C6.   Can I use PCIe x4 and XAUI simultaneously?

[Altera_Forum]

--- Quote Start ---  Hello!  I have 5CSXFC6D6F31C6.   Can I use PCIe x4 and XAUI simultaneously?  --- Quote End ---    According to the handbook, I came to the conclusion that answer is no.   Device has nine channels.  PCIe x4 requires all ( 3 ) channels fron GXB_L0 ( Сh0 - Ch2 ) and 1 channel from GXB_L1 ( Ch3 ). Also, one channel ( Ch4 ) from GXB_L1 is needed as CMU PLL.  XAUI requires all ( 3 ) channels from GXB_L2 ( Ch6 - Ch8 ), 1 channel from GXB_L1 ( Ch5 ). And also need channel for CMU PLL. But we have not left channels.   Am I wrong?

[Altera_Forum]

Cyclone V support FPLL as TX PLL feature. 

Maybe you can use 1 of the FPLL to create 1.5625GHz Fast clock for XAUI? :p Please check for the datasheet what is the MAX frequency the FPLL can support?

[Altera_Forum]

--- Quote Start ---  Cyclone V support FPLL as TX PLL feature.  --- Quote End ---   Yes, in the "Upcoming Cyclone V Device Features" it is written that  "PMA clock output (fPLL as transmit PLL)" is currently supported.    --- Quote Start ---  Please check for the datasheet what is the MAX frequency the FPLL can support?  --- Quote End ---   Yes, fPLL Serial Data Range is from 0.611 Gbps to 3.125 Gbps.    --- Quote Start ---  Maybe you can use 1 of the FPLL to create 1.5625GHz Fast clock for XAUI? :p   --- Quote End ---    The most important question is how to make it? :) When I am generating XAUI Megacore function I can choose only CMU PLL type.

[Altera_Forum]

I'm not sure you are using which QII version. 

In CV Native PHY GUI, you should enable the "Use external PLL" option if you want to use fPLL a transmit PLL feature.

[Altera_Forum]

--- Quote Start ---  I'm not sure you are using which QII version.  --- Quote End ---    Sorry, I am using QII 13.0.0 Build 156.    --- Quote Start ---  In CV Native PHY GUI, you should enable the "Use external PLL" option if you want to use fPLL a transmit PLL feature.  --- Quote End ---    Unfortunately, there is no such option In "XAUI PHY v13.0" and "Cyclone V Hard IP for PCI Express v13.0" Megacore functions.

[Altera_Forum]

Oops...I'm not aware of you are using megawizard XAUI soft IP. 

Unfortunately, you not able to use this option unless you build your own XAUI IP by using native phy ip.

[Altera_Forum]

--- Quote Start ---  Oops...I'm not aware of you are using megawizard XAUI soft IP. Unfortunately, you not able to use this option unless you build your own XAUI IP by using native phy ip.  --- Quote End ---    Thank you! Is there a guide, which describes how to set up a Native PHY in XAUI mode?

[Altera_Forum]

Basically, Native Phy is just a transceiver/Physical layer used in XAUI protocol. 

In order to fully compliance the XAUI protocol, you need to write a a soft logic such as deskew fifo to compensate the lane skews, rate matcher to compensate the ppm difference and other blocks that required by XAUI protocol.