Cyclone V PLL outclock is zero

[Altera_Forum]

Hi everyone 

I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :(  I build my project on Cyclone V GT FPGA development kit, and I use Quartus 13.1 update 4 Full version.  I use the golden_top example from Altera and then build my project including the Qsys system and the PLL on it. I have been struggled with this issue for a week and I cannot do anything else till it get solved. Can someone help me out

[Altera_Forum]

If the PLL doesn't produce anything check the reset signal (and the locked signal). As most designs use synchronous resets make sure that the clock domain where the reset comes from is not the same as the output clock.

[Altera_Forum]

can you be more specific.  

I use signalTap and the locked signal is zero, does it mean my PLL has lost lock.

[Altera_Forum]

The locked signal should go high if pll is locked to the reference clock and you are safe to use it. 

If it stays low, there is obiously something wrong.  Check the reset signal of that pll. Typically it is high active!  I also would advice you to connect the locked- and reset-signal together with the clock to some pin header and analyse it with an oscilloscope.

[Altera_Forum]

Thanks a lot, supernode.  

I have just fixed this problem by alternating 125Mhz clock with 100Mhz clock input of PLL. I think the reason for this issue is that 125Mhz is GPLL-req's External term.

[Altera_Forum]

You must specify the clocks in the megawizard according to your real clock frequency that is going into the PLL. Otherwise the output clocks will have a unwanted frequency or the PLL will not lock. 

If you have 125MHz on your board, then set it to 125!  External termination (I think that is what you meant?!) depends on your board design and can be adjusted via the assigments editor (I think Cyclone V devices have internal termination resistors for LVDS inputs). Not terminating a clock signal may result in unwanted signal distortion. Make sure your PLL sees a quite good incoming clock signal. Measure the clock signal at the FPGAs clock imput pin.

[Altera_Forum]

Well, I have 125Mhz on board, so the clock set in megawizard is 125Mhz and the output is zero. However, when I use 100Mhz (of course I change the reference clock frequency in Megawizard to 100Mhz too), I got the desired output. 

I attached the table of on-board oscillators which I get from reference manual of Cyclone V GT FPGA development kit. Can you find out any thing from this. Thanks in advance. https://www.alteraforum.com/forum/attachment.php?attachmentid=10072  https://www.alteraforum.com/forum/attachment.php?attachmentid=10071   One more thing, what should the Operation mode (in megaWizard) in this situation be? Thanks again

[Altera_Forum]

Check if you use the correct clock input (clock pin). As those fpga boards typically have programmable clock buffers check the incoming clock frequency. 

  Use Normal mode. Please start reading the documentation of your device. Things like PLL modes are described there in detail.

[Altera_Forum]

I got it, thanks a lot supernode. :D