It seems I have encountered a Problem with PLLs in Cyclone V devices,when the PLL is operating in "normal" compensation mode. According to the Cyclone V manual, a PLL in normal mode should compensate the delay of a global clock network in such a way, that the clock routed via the global network should reach all the destination registers (almost) co-incident to the external reference input of the PLL. For Cyclone 1 and Cyclone IV devices, that seems to work as expected. But for Cyclone V devices, the TimeQuest analysis says that this does not work at all. Even worse some tests with real Cyclone V hardware suggest that TimeQuest is not (completely) wrong: It seems that somehow the "normal" compensation mode does not work as expected. I put two mini example designs for Cyclone IV and Cyclone V here: http://www.lauterbach.com/support/static/altera_tco_tests.zip Both designs were compiled with Quartus II 16.1.0 (Build 196 10/24/2016). My guess is, that the Quartus II version, does not really matter (I expect the problem to appear with any Quartus II version). For both designs you can get a timing analysis, by opening TimeQuest and then running "Script->report_timing.tcl". I am particularly interested in the slow and fast corner "WITH PLL" panels. The part of the design I am interested in does this:
GLOBAL CLK NET iClk -> PLL ----------> I/O Register ----> Pin rDataB oDataBI am measuring the delay from a rising edge on iClk to the output on the Pin ( oDataB ) ; so the clock-to-output time. Note: iClk is supposed to have 50Mhz, the PLL output is also 50Mhz; the PLL is just used to compensate the delay of the global clock network. The essence (the part which I am worried about) is this: For Cyclone IV devices TimeQuest reports a clock path delay (from the input clock reference pin to an I/O register) of: - fast corner: -0.298 - slow corner: 0.214 This is what I would expect: The compensation keeps the delay close to 0ns. For the fast corner you get a negative "delay", because the PLL over-compensates. For Cyclone V devices TimeQuest reports the same kind of clock path delay as: - fast corner: 0.591 - slow corner: 3.219 Especially the slow corner seems to indicate, that the PLL is not compensating much. Now I am wondering what am I doing wrong ? Is this a known issue with Cyclone V devices ?