Cyclone V POR trip level

[Altera_Forum]

1. I need to investigate the FPGA status when vcc(1.1V) become 0.1V~1.0V, 

so I want to know the Cyclone V POR trip level?  2. I want to use STM32 to monitor the nSTATUS pin to know whether FPGA reset or not, use polling method. so I want to know how long will nSTATUS stay low level after FPGA reset?

[Altera_Forum]

Hi, 

   --- Quote Start ---  Cyclone V POR trip level?  --- Quote End ---   Power Supplies Monitored by POR, should meet 80% of its last power supply. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf http://www.ee.ic.ac.uk/pcheung/teaching/e2_experiment/c5%20handbook%20v1.pdf    --- Quote Start ---   how long will nSTATUS stay low level after FPGA reset?  --- Quote End ---    For Cyclone one FPGA resets the configuration device by pulsing nCSO, releases nSTATUS after a reset time-out period (about 30 μs), and retries configuration. https://www.altera.com/en_us/pdfs/literature/hb/cyc/cyc_c51013.pdf or Cyclone 5 refer Cylone5 handbook.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)