Cyclone V Quartus II 14.0 partial reconfiguration

[Altera_Forum]

Hi All,  

 I'm about to embark on my first partial reconfiguration project using the Cyclone V with Dual ARM core and the Quartus II 14.0 software. I'm just hoping someone can point me to the correct documents for this (or has any useful titbits from their own experiances)? I've found lots of support for the Stratix IV device using Quartus II 13.1 but I'm not sure if the same applies.   Looking forward to your responses!  Cheers   Alex

[Altera_Forum]

Hi Alex, 

 I am working on my first PR project as well at the moment, and I also have the problem of finding a tutorial or example about it. I am wondering if you had found any useful information about using Quartus for PR. It seems that there are not so much information about Altera partial reconfiguration on the Internet. Thanks!  Best regards,  Tim

[Altera_Forum]

--- Quote Start ---  Hi Alex,  I am working on my first PR project as well at the moment, and I also have the problem of finding a tutorial or example about it. I am wondering if you had found any useful information about using Quartus for PR. It seems that there are not so much information about Altera partial reconfiguration on the Internet. Thanks!  Best regards,  Tim  --- Quote End ---    This is a fun one. Looking at the FPGA Manager driver, I'm seeing that the Xilinx Zynq driver has been written to support it, but not the Altera driver. The HPS definitely supports it (page 35 of the Cyclone V HPS manual, for example), but the socfpga FPGA manager driver still doesn't. I wonder if the Altera dev team has gotten around to this yet?

[Altera_Forum]

Hi, 

 Apologies for not responding to my own thread! It has taken a long time to get my head around this problem. Out of interest which particular variant of the Cyclone V SoC are you trying to enable partial reconfiguration on (it does make a difference!)  Following the Altera SoC Developers Conference, Frankfurt in October I have released a paper regarding some of the work I have done on this topic which may be found here:  https://www.altera.com/events/northamerica/altera-soc-developers-forum/technical-content.html#innovate-with-soc-fpgas----synchronized-networking-and-processing-on-an-soc-fpga It is the "developing and implementing dynamic partial reconfiguration for pre-emptible context switching and continuous end-to-end dataflow applications" presentation and paper. Which may help to give you slightly more understanding of what I have achieved using the DE1-SoC.   Hope some of this helps.   Alex

[Altera_Forum]

--- Quote Start ---  Hi,  Apologies for not responding to my own thread! It has taken a long time to get my head around this problem. Out of interest which particular variant of the Cyclone V SoC are you trying to enable partial reconfiguration on (it does make a difference!)  Alex  --- Quote End ---    Okay, that is an absolutely fascinating model. I've not seen those before-- but it definitely would be a nice feature to have in the fabric. This is essentially adding a boundary-scan feature to every LUT, though, which makes me wonder about its feasibility and resource usage in current designs. Looks good though.  But what this doesn't solve is the fact that the FPGA Manager itself is able to accomplish partial reconfiguration and the driver isn't written for it... were you able to work on this, or was everything done using a custom AXI module?  Thanks! Fascinating read.