I am currently working on a reconfigurable PLL in my design. After lots of research and experimentation, I am slightly confused with the results I am seeing. Specifically, the PLL has issues locking for a lot of frequencies I have tried to generate. I have a summary below of what I have learned and some of the configurations that I have tried so that you guys know where I am coming from. I had a couple of questions that I would like to ask.
- What is the correct way to set m, n, and c (and m_frac) to change the output frequency? Should we set m and n to constants in our application and only vary c (and m_frac) to get our desired output frequency or can we vary all three of the variables to achieve our desired output frequency as seen in this forum?
- I have found this forum post that suggests changing M, N, and C on the fly using three separate for loops. The issue that I run into with this configuration is that we lose lock indefinitely on certain configurations of M, N, and C, but not for others. http://www.alteraforum.com/forum/showthread.php?t=32135
- If it is it okay to change M, N, and C on the fly, do we need to reset the PLL, the reconfigurable PLL, or both to achieve lock and how?
- How do the DSM settings affect a fractional reconfigurable PLL and what parameters should we look at and change in QSYS when using this kind of PLL?
- Maybe, you could explain, in brief, the best method of changing the output frequency of a reconfigurable PLL during runtime?
- Is there a document that you could link us to that further explains how to configure those three settings (channel spacing, fractional carry out, and DSM order) for our FPGA or explain to us how they work?
my understanding of reconfigurable pll’s I am currently working on a reconfigurable PLL. The Altera chip that I am currently programming for is the Cyclone V 5CSXFC6D6F31C8NES using Quartus 13.1.0. From my understanding of the Altera PLL Reconfig MegaFunction, there are two options for reconfiguring the PLL. You can either enable .mif streaming or you can use memory addressing. Currently for our project we are using memory addressing. We are currently using QSYS for our PLL and our reconfigurable PLL to make the connections between the two and we are using a NIOS II processor to do the modifications to the addresses for the reconfigurable PLL. I have also been using page two of the following document for a better understanding of reconfigurable PLL’s along with a good diagram:
http://www.altera.com/literature/ug/ug_altpll.pdf From my understanding of this document (and many others that I have read), there are three main counters. They are listed below:
- N counter – pre-divider counter
- M counter- feedback multiplier counter
- C counter – post-divider counter (referred to as K and V in this document, but C everywhere else)
I know that you can have several C counters as well, but for our purposes, we have only been modifying the C0 counter. From what I have read, there are several considerations that you must keep in mind when modifying the registers to reconfigure your PLL. You have to make sure that your frequency is able to lock. If you modify M or N, you run the risk of losing your lock because you might get outside of the acceptable Fvco range. Apparently if you modify C, you will not lose your lock because C in the diagram does not affect Fvco. You need to also make sure that you modify the different counters using the following equation to make sure that you get your desired frequency:
Fout = Fin * (M/(NxC))
Fout = output frequency
Fin = input frequency
I also use the following equation for determining the M and N counter values to make sure that they are in my acceptable range of Fvco:
Fvco = Fin * (M/N)
I also use page 27 of the following document to figure out my acceptable range of Fvco:
http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf Since I am using a speed grade of C8, my acceptable Fvco is 600-1300MHz. I do also realize that there is a Fvco divider setting that will divide my range by two allowing me to have a range of 300-650MHz, but we have been configuring our Fvco towards the upper bounds so that we can have more precision on our clocked output frequency.
different approaches of my project On all of the approaches, we have used a fixed 50MHz clock, we do not switch between multiple input clocks, and we are using an Integer-N PLL instead of a Fractional-N PLL.
The first thing that we tried to do in making a reconfigurable PLL was write some C++ code in NIOS II that would essentially run three for loops for M, N, and C along with the equation Fout = Fin * (M/(NxC)) to get our desired frequency. We would send it a desired frequency and it would run through all of the different configurations for the three different counters until it found a configuration that would give us the desired output. The issue that we had with this configuration is that it seemed like we were not able to lock all of the desired frequencies that we would have liked to. We used a range of M, N, and C from 2-510 (since it is 512 bits wide for us). We had no issues correctly writing the data to the registers. In our program, we used an approach that is similar to one of the reference C design files that Altera provides (which is the attachment PLL_RECONFIG.txt since I cannot attach a .c file), in which we would first write the mode register to one, write our three counters to their respective registers, and then write a one to the start configuration address, then use a do/while loop that determines whether or not the frequency will lock. Like I stated previously, I believe that this approach did not work due to the M and N counters being modified outside of the Fvco locking range. We are using page four and five of the following document to properly configure our addresses:
http://www.altera.com/literature/an/an661.pdf Our second approach was to then test the above program with a break out of the do/while loop after a certain number of clock cycles to help see which counter settings would lock and which ones did not for a specific frequency.
Our third approach was determining M and N so that it was in the Fvco locking range and then keeping those two counters constant. From there, we would only vary the C0 counter to try to get our desired frequency. Even though this approach works, we need a way to gain more accuracy, especially for higher frequencies. The lower frequencies are much more accurate than the higher frequencies.
We have two more ideas that we are currently testing. Our first idea is similar to our first approach in which we use three for loops for the different counters and try to get the correct output frequency that way. It differs in the fact that we are only going to use M and N values that are in the Fvco locking range instead of a range of 2-510. Our C0 counter will be using a range of 1-510. Our second idea is to try and use a Fractional-N PLL, set our M and N values so that they will not change, and then only vary C0 and M_frac so that we can get the precision that we need for our design. The issue that I am running into with this design is that I am having trouble finding documentation on the Altera PLL Megafunction for channel spacing, fractional carry out, and DSM order. I need to know how to configure these settings properly, but I do not see it in the following documentation:
http://www.altera.com/literature/ug/altera_pll.pdf I was wondering if there was a document that you could link us to that would further explain to us how to configure those three settings for our FPGA or explain to us how they work? I have spent several hours looking up the information through google and Altera’s website, but I have not had any luck. I have seen forum posts that say that they use a third order DSM for the least amount of jitter, but I do not understand how to properly configure the Delta Sigma Modulator to suit our needs. The closest that I have found to explaining DSM is in the following document:
http://www.altera.com/devices/fpga/stratix-fpgas/stratix-v/overview/fpll/stxv-fpll.html Even though this explains how it works, it does not give me details on the configuration settings that I need to set in QSYS to get my program to run properly.
Thank you for your time!
