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21615 Discussions

Cyclone V SOC Maximum Speed

Altera_Forum
Honored Contributor II
‎06-16-2015 02:47 AM
1,770 Views

Hi, 

 

I'm trying to build SPI master with SCK speed as high as possible. For some reason, my target SPI SCK is 166MHz. I'm using DE0-NANO-SOC board running Linux socfpga 3.13. The software controls SPI core through memory mapping (MMAP) method. I created Altera SPI Core with Avalon bus in the FPGA fabric connected to LXAXI bus and Altera PLL. The LWAXI bus clock is also driven by PLL output 0 at 100MHz. SPI core is driven by PLL output 1 at 210MHz. This produce SPI SCK speed of 105MHz. By trial and error, this seems to be the highest speed I can go. 

 

Is there any specification about what is the highest internal bus speed and highest I/O speed for this device? I can't find it in the datasheet. Anyway to further push up the speed? Right now my SPI core is connedted to the DQ physical pin in bank 3A with 3.3LVTTL standard. 

 

1. Can the speed be increased if I change the physical IO to other pins / standard? 

2. Can the bus speed be increased if I change LWAXI to AXI? 

3. DE0-NANO-SOC is based on Cyclone V SE speed grade 6, if I change to Cyclone V SX / ST, Can I increase the speed further? 

4. Any other suggestion to improve the design please? 

 

Thank you in advance.
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Altera_Forum
Honored Contributor II
‎06-16-2015 04:46 AM
891 Views

 

--- Quote Start ---  

Hi, 

 

Is there any specification about what is the highest internal bus speed and highest I/O speed for this device? I can't find it in the datasheet. Anyway to further push up the speed? Right now my SPI core is connedted to the DQ physical pin in bank 3A with 3.3LVTTL standard. 

 

1. Can the speed be increased if I change the physical IO to other pins / standard? 

Thank you in advance. 

--- Quote End ---  

 

 

Hi, 

 

I believe there is no spec on the max IO data rate available in the device datasheet currently. To further increase the data rate, you can try to play around with different IO standards, current strength and slew rate to see if can further boost the data rate.
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Altera_Forum
Honored Contributor II
‎06-16-2015 09:08 AM
891 Views

Hi Bfkstimchan, 

 

How about the bus speed? How can we know what is the maximum clock speed for F2H / H2F AXI / LWAXI buses?
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