Cyclone V SoC family HPS EMI device support

[BrianSune_Froum]

Dear Intel and all,

According to emi_ip-683841-666668.pdf

"4.3. SDRAM Controller Memory Options
Bank selects, and row and column address lines can be configured to work with
SDRAMs of various technology and density combinations.
Table 26. SDRAM Controller Interface Memory Options"

The maximum page size is only 1k, do 2k die is allowed?

Thank you

[AdzimZM_Intel · Accepted solution]

Hi brian8sune,

Using the memory component with 2K page size should be okay.

But you cannot implement the interface as DQx16bit since the IP only allow for DQx8bit configuration.

Therefore, you need to route the memory as 8 DQ bit per DQS group.

Regards,

Adzim

[BrianSune_Froum]

Hi Adzim,

Of cause, for DDR3 always route in byte form with DS/DM/DSQ group byte data bit swap allowed.
So I guess this is settle and clear thank you