Cyclone V active serial configuration w/ EPCS128 failure.

[Altera_Forum]

Hi all, 

 I have run in to an issue on my custom board that I can't seem to figure out.  - The board has an active serial configuration setup. The EPCS128 is programmed by an external programmer and then put into a socket on the board. - The configuration cycle starts (I can see it on the scope), and I can see the FPGA send the read status command and get it back, and send the read device ID and get it back. - The FPGA then initiates a fast read of the EPCS and I can see the data beginning to stream.   The problem occurs when the FPGA deasserts nCS before all the data is done being streamed, which causes nSTATUS to detect an error, which causes it to pulse low, which restarts the configuration cycle.  Some other info. I am using ASx1. DCLK is 12.5 MHz. All voltages are at 3.3V for configuration. I am using Quartus II v15.0. The external programmer I am using is a ChipProg481. This was meant to be a stand alone board so there is no usb-blaster header on to try program that way.  DCLK has some high frequency ringing, but nothing that causes a dip below 3V and a rise above 0.3V, so well within the spec of both devices.  Has anyone encountered a similar issue. Any help is appreciated.  Thanks,

[Altera_Forum]

It sounds like it's detecting an error in the bit stream. It checks the CRC of the bitfile at the end. If there is an error it will retry. It may be a clock integrity issue. You want to check on the clock signal to the EPCS to make sure it's clean, and maybe work on the termination a bit. 

 Pete

[Altera_Forum]

Thanks Pete. 

 I have looked at my DCLK, and there was some ringing on it. I was able to insert a termination resistor at the pin of the EPCS and that cleaned up the clock. I am still having the same problem though. I have tried several IC's and several boards to ensure that that was not the issue. It is consistent across all five of them. I tried adding both series and parallel capacitance to slow down the edges, but that just made it worse.  At this point, I am stumped.  Gavin

[Altera_Forum]

I'm no expert on AS programming and what could cause the sequence to abort/restart, but I'd be looking at the contents of the EPCS128 as the possible source of the problem. Are you loading the .rbf file from Quartus into the EPCS128?

[Altera_Forum]

Have you looked at the contents of an epcq programed from a .pof by quartos? 

It might be that you aren't writing the data correctly. In particular are you remembering to bit-reverse the bytes from those in the .rbf file?

[Altera_Forum]

Good catch, forgot about the bit reversal.

[Altera_Forum]

I am loading the EPCS with the .pof generated from quartus. I have tried having it generate it directly and using the conversion utility from the .sof. I did just try using the .rbf file reversing bits and still getting error. Do I need to reverse the .pof as well?

[Altera_Forum]

Thank you everyone! I bit reversed my .pof and it worked! You guys rock.