Dear all,I am using a Cyclone V 5CSXFC6D6F31C6N on a terasic sockit (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=167&no=816&partno=1) developer board to produce two coherent clock signals via the PLLs of the FPGA. To get those clock signals of-chip, the terasic xts-hsmc (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=67&no=129)break-out board is used. Looking at the resulting signals via an scope (KeySight DSO3054T) using a high input impedance, they look quite messy. Typically, these kind of signals are 50 Ohm terminated. So it could be that the messyness of the signals is a result of reflections due to poor termination. However I am not sure if the FPGA can drive a 50 Ohm load. Most pins could only proivde something like 8 to 12 mA. Using the 2.5 Vpp output swing to drive a 50 Ohm load is than asking for problems. Due to board limitations, the output of the PLLs is routed via PINs A10 and A11. According to quartus and the pin information of altera (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-v/5csxfc6.xls) these pins have the special function of FPLL_TL_CLKOUTn (A10) and FPLL_TL_CLKOUTp (A11). I think (according to the Technology Map Viewer of Quartus) that the pins are driven bij a buffer called "IO_OBUF", although I could not find any additional infromation about this buffer on the internet. Based on the special function I think pins A10 and A11 could drive a 50 ohm termination impedance, because it is quite standard to use a 50 ohm transmission line and 50 Ohm termination impedance. However I have been googling, reading, and searching the web for over a day and have not yet found any information which confirms or rejects this assumption. Does anyone here knows if I could safely terminate pins A10 and A11 with a 50 Ohm impedance? Thanks in advance :) With kind regards, Wobbert
I'm not sure if the A10/11 pins can drive those 50ohm external loads. But you could take a look at the Altera OCT IP which can drive upto 240ohm external loads.https://www.altera.com/en_us/pdfs/literature/ug/ug_altera_oct.pdf I'm not sure this will help you, but its an On-chip termination IP thats used for memory signals drive and terminations.
There are several IO standards that can drive single ended 50 ohm or differential 100 ohm lines.The preferred termination scheme to achieve full 2.5, 3.0 or 3.3V CMOS level would be a 50 ohm source side termination and high impedance load side termination. You can also feed a 50 ohm load with the 50 ohm transmission line, resulting in halved receiver level. What's your intended load impedance? For the 50 ohm source side termination, you'll usually place a series resistor that adds with the driver output impedance to 50 ohms. Expect a driver output impedance around 15 ohms for high drive strength. Detail information (pin I/V characteristics) for different IO standards can be found in Ibis files. --- Quote Start --- Most pins could only provide something like 8 to 12 mA. --- Quote End --- Don't confuse the CMOS/TTL drive strength specification with maximal output current. You should however keep the maximum ratings in device datasheet.
--- Quote Start --- What's your intended load impedance? --- Quote End --- I was measuring my clock signals via an oscilloscope at High Z. I saw some shabby signals so I expected this to be the result of reflections due to bad termination (1M instead of 50 Ohms). However the professor supervising my project didn't thought the clock signals were that shabby. I want to drive an ADC with the clock signals. I expect the ADC to have a high impedance clock input, although the datasheet does not provide any info about the clock input impedance of this ADC. So actually there seems not to be any problem at all (due to the high impedance nature of the ADC clock input). Besides that, the datasheet I found during a quick search (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf) states that the maximum DC pin current 40 mA's is. That is a lot more than the 16 mA for a certain driving mode. So maybe there are no problems after all. Thanks for the info!
When measuring a clock (or any high frequency signal) with a scope, be careful with the ground connection. If your scope probe ground connection is far away from the signal you are measuring, it can appear more distorted than it actually is.In your case I think a 33 ohm resistor in series, close the the FPGA, will be enough. Yes there will be a reflection when the signals arrives at the ADC, due to the high impedance on the input, but the reflection will just go back towards the FPGA and be absorbed by the serial termination there. As far as the ADC is concerned, the clock signal should look clean.
ADC clock input is usually capacitive, the pin capacitance should be specified in datasheet.Don't know what's the required clock input level. If you need full TTL/CMOS voltage swing, e.g. 2.5 or 3.3Vpp, source side termination as mentioned in post# 3 can achieve almost perfect signal shape. If termination is needed at all depends mainly on the transmission line length between FPGA and ADC. Some ADCs have differential clock inputs that can be best driven by LVDS IO standard with 100 ohm load side termination.