Cyclone V custom board VCCIO puzzling behavior

[BrianSune_Froum]

Dear Intel and all,

I am working on Cyclone V soc 5CSEBA5U19C8N.
There is a very puzzling VCCIO behavior.
According to "Cyclone® V Device Family Pin Connection Guidelines
PCG-01014-3.2".

Any 3.0 below VCCIO must use a VCCPD with 2.5V.
I am supplying VCCIO of bank 3B+4A with VCCPD 2.5V and the VCCIO is using 1.2V.
However when measuring the VCCIO rail the voltage raised to almost 1.5V.

Before the FPGA chip is applied the voltage rail is able to measure clean 1.2V which eliminates the DCDC issue.

This is very puzzling, please FAE or Intel employee support.

Thank you

[FvM]

Hi,
I designed with Cyclone V nine years ago but don't remember a similar issue.

Is VCCIO 1.2V node completely floating or has it relevant load? Presumed it's true that Cyclone V is actually driving out on VCCIO due to VCCPD leakage current and not powered by a different path, I would try to determine the actual leakage current, both for nominal 1.2V and 0V level. There's no leakage specification in datasheet, I would not exclude a small leakage current, e.g. below one or maximal a few mA which could be easily dropped by a pull-down resistor.

Of course, if such effects exists, they should be mentioned in datasheet and user manual.

Regards
Frank

[BrianSune_Froum]

First you mentioned you had design Cyclone V before.
I make the following assumptions that should make sense and should "NOT" be violate the device inherent silicon design.

1) according to handbook:
In the Cyclone V devices, all I/O banks have individual VCCPD with the following exceptions:
• Cyclone V E, GX and GT devices:
• Banks 1A (if available) and 2A share the same VCCPD.
• Banks 3B and 4A share the same VCCPD.
• Banks 7A and 8A share the same VCCPD.
• Cyclone V SE, SX and ST devices:
• Banks 1A (if available) and 2A share the same VCCPD.
• Banks 3B and 4A share the same VCCPD.
• Banks 6A and 6B share the same VCCPD.

So the rules should follow VCCPD = 2.5V if VCCIO <= 2.5V else VCCPD === VCCIO

2)  the same puzzling bank is tested with 1.8V 2.5V which shows no such behavior on the same gear.

3) So if VCCPD is causing such issue why 1.8V is not having such behavior? aka increase on voltage.

[BrianSune_Froum · Accepted solution]

There are new measured data.

If I attached a simple 10k resistor to the 1.2V rail. it will drop back to normal 1.2 range.
But the loaded /w 10k is still measuring 40mV higher than unloaded DCDC w/o the FPGA chip.
So there are some leakage current inside the diode path? from VCCPD to VCCIO?

[FvM]

Hi,
result sounds promising, a lower pull-down value like 500R or 1k can hopefully cut unwanted VCCIO leakage. I'd however expect a statement from Intel support, it might be a known problem. Particularly we should get specification of maximal leakage current.

A final question, can you exclude that the problem is caused by a partly damaged device, e.g. due to ESD?

[BrianSune_Froum]

No this theory don't holds. If it is damaged by ESD why only 1.2V is able to trigger a higher voltage?
I will highly expected :
A internal VCCPD diode is leakage due to VCCIO-VCCPD high at VCCIO low.
As V(diode) breakdown aka current increase when voltage increase aka basic diode IV model.
However if a ESD had break the barrier then no matter it is what voltage level. 

I do measured via diode model on meter and all VCCPD and VCCIO related group is almost same.

The data last I got is that around 100uA to 1mA on VCCIO rail can easily remove the voltage increase behavior.

[BrianSune_Froum]

@JingyangTeh_Altera 

Any internal FAE or engineers could explain this issue?

[BrianSune_Froum]

@FvM 

I am afraid even with more board had assemble the same issue are kept. without any load aka resistor or other IO driver sink/source from any pins. There is always a raise voltage on 1.2V VCCIO /w VCCPD 2.5V from 1.2V to 1.45

[FvM]

Hi,
I understand that the effect is unexpected. However VCCIO supply of most FPGA boards will absorb uA range leakage currents unnoticed, thus it might be that observed VCCD to VCCIO leakage current is quite common.

Regards
Frank

[BrianSune_Froum]

@FvM 

I do  think this is common.

For example Kintex 7 one IO bank is completely empty on any load yet there are no such thing happened.
I think this is the inherent silicon design fault on Altera FPGA.

First got to understand the VCCPD and VCCIO what actually means rather than guessing diode etc.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/power/pow-overview.html

I don't think the leak could introduce such result.

1.2 to 1.5 is 300mV can't explain how could it reach that level.

[FvM]

Hi,
I don't expect that this (apparently flawed, unclear transistor gate/source connection) principle schematic is helping to identify possible leakage paths between VCCPD and VCCIO node.

Not sure what you are trying to achieve, why has VCCIO 1.2 V supply high impedance in your design? Is there anything against applying a moderate pull-down resistor, e.g. 1k at VCCIO 1.2V rail?

Regards
Frank

[BrianSune_Froum]

@FvM 

Very simply, just like FMC slot ->Before any slot cards are inserted to the slot it is open.

Then an open slot will introduce a voltage as this ticket mentioned.

Why waste power on unnecessary resistor when it should not be the case.

Any development board could experience such issue before the slot is use.

So unless there is a good explanation  VCCIO on 1.2V or 1.5V is risky as it introduce unexpected raise of VCCIO rail.

There are no deep investigation on driver IOs in purpose of the empty slot IO bank via dummy IO on HDL design. 

So far there are no official response on this issue, and I can't see this is related to any external damage like ESD etc.

As for the leakage, this is also pure guess on diode or any pass-gate whatever leakage from the beginning, but after study more documents this is not the actual case.

So applying resistor to remove the raise on voltage rail is just covering the issue without really knowing what is the problem.

Such solution is just introduce lifespan hazard.

### More document study

The group of the FMC slot is 14 sets of LVDS.

Assuming 28 * 30uA = 840uA.

Assuming 1.2V at 840uA = 1k43 ~ =1k5

But this only applied to IO undriven as input case.

If my understand is correct. the default Quartus sets the undriven IO to input /w small pull-up.

However, even setting the project to output driven to ground only makes 10mV different.

So there must be s.t. missing from first place.

[FvM]

Hi,
I don't yet understand the relation to "open FMC slot". Or are you feeding VCCIO externally? Unusual, but no problem according to Cyclone V hot-socketing feature.

LVDS I/O standard for Cyclone V uses 2.5 V supply, How is LVDS signal related to 1.2V VCCIO. 

You have previously reported VCCPD to VCCIO leakage, there should be no relation to I/O pin leakage. Or do you suspect that VCCIO 1.2 V is raised  due to I/O voltage exceeding VCCIO rather than VCCPD? In this case, I/O pin leakage can matter.

Just for clarification:

- What's the configured I/O standard in the affected I/O bank(s)?
- Are I/O pins driven externally above VCCIO?

Regards
Frank

[BrianSune_Froum]

@FvM  

First appreciated trying to help but I guess you had tried all your best.

But with all due respect.

Your questions make me feel stupid.

FMC LPC or HPC card slot is a very standard.

I had never hear LVDS is 2.5V only.

I am afraid your comment just review you had no idea on any hardware designs nor standard.

@khtan  @JingyangTeh_Altera 

I guess wait for vendor responses or guidance are a better choice.

[FvM]

---

@BrianSune_Froum wrote:

I guess wait for vendor responses or guidance are a better choice.

---

Absolutely. After your latest post, I'm not even sure if we see irregular device behaviour at all or just operation beyond Cyclone V specifications.

As I'm working with Altera FPGA quite a long time, e.g. Cyclone V since 2014, I'm taking some specifications as granted, not considering that they might be misunderstood.

[Farabi]

Hello,

I am taking over this case from previous owner.

How many devices you see the similar behavior?

This could possibly caused by VCCPD to VCCIO leakage current.

Do you have any undriven IOs with weak pullups?

Please make sure no VCCIO rails unconnected/unused especially FMC slots.

Can use pulldown resistors to stabilize the voltage.

regards,

Farabi

[BrianSune_Froum]

@Farabi 

Thank you, finally there is FAE or staff can handle this ticket.

1) All
2a) for a development board form factor how could you expect all slot MUST used in any situations?
So of cause the situation happens on FMC slots is not used.
2b) As mentioned even setting this cannot see the effect is removed.

So this control on the EDA is so puzzling for what purpose?

3) as mentioned in this very beginning of this ticket, the adjustable DCDC buck converter is tested w/o the FPGA is applied and no voltage raised or out-off-range measurements are found. This is introduced by the FPGA Chip itself.

### add ups

** if configurated the unused pins to ground + output.
tested the pins do load to ground.

However, the power rails shows very low different 10-5mV different yet still raised a lot from 1.2 to 1.47.


Bests,

Brian

[Farabi]

Hello,

1- You observed voltage increase at VCCIO power rails. How about the IO signals within the impacted VCCIO banks? Do you observed voltage increase as well?

2- Do this observation impacted any functional behavior of the device? like design failure, FPGA temperature increase etc?

regards,

Farabi

[BrianSune_Froum]

@Farabi 

1) yes both VCCIO and the FPGA-IO on the victim banks. However the VCCIO is higher than IO about 20-40mV.

2) Design failure <- not fully understand, temperature increase (cannot tells because w/o HPS running the system total power is less than 1.3W)
If needed can run a IR image to check hot spot but don't think this is helpful due to ~100mA on 12V input.
The design had individual power rail voltage+current sense yet minimum current range is ~=0.217 mA .

1mA is measured and print on linux hwmon, not sure this is out of range. (no extra load resistor is added as well)

Extra info:

Currently the DCDC is set to 1.8V no extra resistor or load show no issue.
So it is happened on 1.5V or below VCCIO standard.

[BrianSune_Froum]

@Farabi 

Any data on the leakage and what is root causes of such leakage?

Thank you

[Farabi]

Hello,

Let me check with internal team.

rgards,

Farabi