Cyclone V dedicated flash pins with generic serial flash interface

comccmoc · ‎10-17-2022

I am getting "Illegal constraint of I/O pad" errors when attempting to connect a GSFI IP to top level I/O corresponding to the NCSO, DCLK, and DATA[3..0] pins, even though I have it set in the GSFI IP to "Disable dedicated Active Serial Interface" and "Enable SPI pins interface." Is there anything else I need to do to use these pins?

Alternatively, if I cannot do this, what can I do in firmware to access these pins in order to write to configuration flash when the firmware is running?

FvM · ‎10-17-2022

Have you set these pins to "use as regular IO" in the device and pin options, tab dual purpose pins?

comccmoc · ‎10-17-2022

Unfortunately, the only things I have listed in that window are Data[15..8] and Data[7..5]. Both are already listed to be used as regular I/O.

FvM · ‎10-17-2022

Sounds like you selected AP rather than AS configuration interface.

comccmoc · ‎10-18-2022

I think I should have AS Configuration selected, as shown below. Is this what you mean? I'm not sure what an AP configuration interface would be.

ShengN_Intel · ‎10-18-2022

Hi,

Check the document link below on Cyclone V configuration pins' Configuration Scheme and I/O Standard:

https://www.intel.com/content/www/us/en/docs/programmable/683375/current/device-configuration-pins.html

Check image below:

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

comccmoc · ‎10-18-2022

Thank you for your reply. I made IO standard changes in the QSF manually as I could not set them in the Pin Planner. I have the following settings for my pins, but unfortunately I'm seeing no change in the error when switching from 3.3-V LVCMOS to 3.0-V LVTTL:

set_location_assignment PIN_V3 -to flash_dclk
set_location_assignment PIN_AB4 -to flash_data[0]
set_location_assignment PIN_AB3 -to flash_data[1]
set_location_assignment PIN_AA5 -to flash_data[2]
set_location_assignment PIN_T4 -to flash_data[3]
set_location_assignment PIN_R4 -to flash_cs_n
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to flash_cs_n
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to flash_dclk
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to flash_data[0]
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to flash_data[1]
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to flash_data[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to flash_data[3]
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"

ShengN_Intel · ‎10-18-2022

Hi,

The configuration pins listed support only fast slew rate and OCT is not enabled for these pins.

Drive Strength (mA):

DCLK 12

AS_DATA0/ASDO 8
AS_DATA1 8
AS_DATA2 8
AS_DATA3 8
nCSO 8

ShengN_Intel · ‎10-18-2022

Hi,

I further found something in the link below under 4-1. Setting AS Interface and User I/O Interface:

https://malt.zendesk.com/hc/ja/articles/4402782200089-Nios-II-Boot-Option-Generic-Serial-Flash-Interface-%E3%82%92%E4%BD%BF%E3%81%A3%E3%81%9F-Boot-%E6%96%B9%E6%B3%95-#h_01FD6W22N6SNTN0FWNEXPTXMJB

Connection with GSFI Flash ROM supports both AS (Active Serial) Interface and User I/O.

For AS Interface, the default settings are fine. And the Tool automatically connects to the AS Interface without the need to explicitly connect to the FPGA external PIN.

For User I/O, enable the "Disable dedicated Active Serial interface" and "Enable SPI pins interface" settings as shown in [Fig.4]. Export the signal that connects to the Flash ROM and connect directly to the FPGA external PIN that connects to the Flash ROM. Also, do not forget to write the timing constraint file (SDC file).

Nios ® II Boot Option ~ EPCQ Flash ~ (using AS IF)

Nios ® II Boot Option ~ QSPI Flash ~ (using User I/O IF)

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

comccmoc · ‎10-19-2022

Thank you for your information. We are in fact foregoing a soft processor and making these Flash writes ourselves. I do have these settings for the Configuration type to be AS x4, the "Disable dedicated AS interface" and "Enable SPI Interface" boxes are checked, the signals are routed from the IP to their top level ports, and these ports have been assigned to the appropriate pins. I only have the option to set the drive strength to maximum, minimum, and 2mA. The Slew rate defaults to 1 (fastest). Could this be an issue with the target platform of Cyclone V?

ShengN_Intel · ‎10-19-2022

Hi,

https://malt.zendesk.com/hc/ja/articles/4402782200089-Nios-II-Boot-Option-Generic-Serial-Flash-Interface-%E3%82%92%E4%BD%BF%E3%81%A3%E3%81%9F-Boot-%E6%96%B9%E6%B3%95-#h_01FD6W22N6SNTN0FWNEXPTXMJB

4-1. Setting AS Interface and User I/O Interface:

For AS Interface, the default settings are fine. And the Tool automatically connects to the AS Interface without the need to explicitly connect to the FPGA external PIN.

If you're using EPCQ flash, can just use the AS (Active Serial) Interface with default settings where "Disable dedicated AS interface" and "Enable SPI Interface" boxes can be left unchecked. Then set the MSEL pins of the FPGA devices to the AS configuration mode.

https://www.intel.com/content/www/us/en/docs/programmable/683419/22-2-20-2-1/flash-access-using-the.html

"Disable dedicated AS interface" and "Enable SPI Interface" only enabled when want to access the general purpose QSPI flash (user I/O) or for Intel® MAX® 10 devices.

Design examples:

https://www.intel.com/content/www/us/en/design-example/714709/cyclone-v-generic-serial-flash-interface-and-nios-ii-booting.html

https://www.intel.com/content/www/us/en/design-example/714711/cyclone-v-generic-serial-flash-interface-intel-fpga-ip-core-reference-design.html

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

comccmoc · ‎11-02-2022

Sorry for the late reply, I have been unable to login for some time.

https://www.intel.com/content/www/us/en/docs/programmable/683419/22-2-20-2-1/flash-access-using-the.html

"Disable dedicated AS interface" and "Enable SPI Interface" only enabled when want to access the general purpose QSPI flash (user I/O) or for Intel® MAX® 10 devices.

I am taking that to mean these settings can be left unchecked because I am on a Cyclone V?

So I have my Generic Serial Flash Interface with outputs to internal signals that just terminate in the file that instantiates them? I believe I have tried that but the fitter does not route them to the dedicated I/O pads.

Maybe I am forced to use Platform Designer with the Nios processor to make this work?

ShengN_Intel · ‎11-02-2022

Ya those settings can be left unchecked if you're using EPCQ flash since not need to explicitly connect to the FPGA external PIN.

May be you can try to use Platform Designer with the Nios processor and refer to the document steps.

ShengN_Intel · ‎10-24-2022

Hi,

Any further update or consideration? Does the problem being resolved?

Thanks,

Best Regards,

Sheng

ShengN_Intel · ‎10-26-2022

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