Cyclone V datasheet states that the maximum data rate "Fhdsr" is 875 MBit/sec with SERDES factor "J" = 4 to 10.However, SERDES megafunction for Cycone V E device accepts 1GBit/sec at SERDES factor of 8. Which one is right? Basicaly, I'm interested in 1GByte/second LVDS input into FPGA using 8 data pairs with x8 SERDES factor each. Many thanks in advance for help with this question.
--- Quote Start --- The datasheet is correct. --- Quote End --- Thansk ted. So, seems like none of low cost Altera FPGAs support that bitrate on LVDS. Unlike SPARTAN... Pity.