Cyclone lll LVDS IO

[Altera_Forum]

Hi, 

 Currently, we are using Cyclone lll FPGA for our application. We plan to interface LVDS output signals with sensor chip. We had assigned LVDS related O/P signal in bank 7 and bank 8(top banks). As per the Cyclone lll handbook, top(bank 7 & 8) and bottom(bank 3 & 4) only support for Emulated LVDS signals while others banks supports for both LVDS and as well as Emulated LVDS signals.  For Emulated LVDS signal interface, is it compulsory to put external 3R resistor network? Presently we had not included any external 3R resistor network with emulated LVDS output signal but we had put only 100R resistor between differential signals. So, my concern is that whether FPGA provide proper signal interface with sensor chip or we need to redesign the board again.  Will appreciate comments.  Best Regards, Mayur Akbari

[Altera_Forum]

Yes, Quartus assumes that was done and any timing analysis will assume it's there. What happens if they're not there? That's one of those things that just isn't characterized. I assume it won't blow up or anything like that, and probably will just need to run a lot slower or something like that, but again, don't really know.  

Also note that a) Emulated LVDS runs slower than dedicated LVDS, as listed in the handbook, b) I find the numbers spec'd to be too high to begin with, i.e. in most situations for dedicated LVDS you can't really close timing at that high of a rate(and you still need to close timing in TimeQuest to be sure). If the receiver had fantastic specs then it's probably possible, but in most cases it will run slower. (I'm not a fan that Fmax is spec'd for I/O, since the frequency is dependent on the specs of both the transmitter and receiver...)

[Altera_Forum]

To ensure the emulated LVDS output can perform as per the specifications, it is recommended to follow the required 3R resistor network. If without the network, then you could try to perform IBIS model simulation to check if the signal can meet the receiver input specification to ensure the interface can work.

[Altera_Forum]

We had four lvds outputs driving a receiver on another board, I got three channels correct but one came of the bottom of the chip and didn't have the 3 R's. It worked but caused the receiver to dissipate a lot of power because the fpga output was driving the 3 volts across a 100 ohm. We used the prototypes that way but redesigned the board to use the correct pins. The drop in power dissipation was noticeable. Fortunately for us the timing was not that critical, we were going for noise immunity. 

 Kevin

[Altera_Forum]

Hi Kevin, 

 Are you using 4 LVDS tx output to drive 1LVDS rx simultaneously? You are doing this to boost the current in the transmission line?   Won't that be sort of unstable? The standard LVDS was suppose to be differential signal with Vcm ~1.25V and Vod ~100-400mV

[Altera_Forum]

No, each output was driving a single receiver in a quad lvds receiver with internal termination. Because the receiver was terminated internally I couldn't remove the 100 ohm resistor so one channel in the receiver chip was dissipating 100mW all by itself. 

I was just commenting about the fact that I got away without using the external 3R termination in our prototypes but I would never ship product that way. We re-layed out the board to move that one channel from the bottom to the side. Everything was cooler after that.