Cyclone with Audio CODEC in VHDL

[Altera_Forum]

Hi everyone, nice to meet you all here.  

 Im working on a project which will take audio input, go through a filter and generate the filtered audio output. In this project, SystemVue (a design software by Agilent) is sued to design a filter and VHDL or verilog codes can be generated by SystemVue. It means that it does not require us to write the ourselves, the VHDL/verilog codes are auto-generated in software. In order to evaluate the functionality and the performance of the designed filter, the generated VHDL files are combined into a single project using Quarrtus-II and is programmed into Cyclone-II FPGA. And finally, an audio signal is input to the audio CODEC on Altera DE2 board, go through the Cychone-II (designed filter) and output it at the audio CODEC.   I have successfully designed the filter that i want and generated the VHDL code already. the problem im facing right now is the generated code actually create the output at the expansion header instead of audio codec. Do you know how to modify the codes that create the audio output at Audio codec instead of expansion header? Im not able to solve this problem because i have insufficient knowledge on VHDL.  Could you guide me through this? Thank you very much.:)     library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity FIR_Fxp1_GNRC is port (   x : in std_logic_vector(31 downto 0);  y : out std_logic_vector(46 downto 0);  rfs : out std_logic;  sor : out std_logic;  reset : in std_logic;  nsi : in std_logic;  clk : in std_logic);  end FIR_Fxp1_GNRC;  architecture aFIR_Fxp1_GNRC of FIR_Fxp1_GNRC is   signal x_pipe : signed(31 downto 0) := (others => '0'); signal M_641 : signed(41 downto 0) := (others => '0'); signal M_1697 : signed(42 downto 0) := (others => '0'); signal M_11 : signed(35 downto 0) := (others => '0'); signal M_3635 : signed(43 downto 0) := (others => '0'); signal M_2816 : signed(43 downto 0) := (others => '0');   signal tap7_add641 : signed(41 downto 0) := (others => '0'); signal tap6_add1697 : signed(43 downto 0) := (others => '0'); signal tap5_add2816 : signed(44 downto 0) := (others => '0'); signal tap4_add3635 : signed(45 downto 0) := (others => '0'); signal tap3_add3635 : signed(45 downto 0) := (others => '0'); signal tap2_add2816 : signed(45 downto 0) := (others => '0'); signal tap1_add1697 : signed(46 downto 0) := (others => '0'); signal tap0_add641 : signed(46 downto 0) := (others => '0');  signal counter_en : std_logic; constant LATENCY : integer := 4;  begin     process (clk)  variable counter : integer range 0 to LATENCY-1;  begin  if clk'event and clk = '1' then  if reset = '1' then  counter_en <= '1';  counter := 0;  elsif nsi = '1' and counter_en = '1' then  if counter = (LATENCY-1) then  counter_en <= '0';  else  counter := counter + 1;  end if;  end if;  end if;  end process;   sor <= nsi and (not counter_en);  rfs <= '0';   InputPipelineStage : process (clk)   begin   if (clk'event and clk='1') then   if (nsi = '1') then   x_pipe <= signed(x);   end if;   end if;   end process;     MultiplierBank : process (clk)   begin   if (clk'event and clk='1') then   if (nsi = '1') then   M_641 <= resize(x_pipe * to_signed( 641, 11 ), 42);  M_1697 <= resize(x_pipe * to_signed( 1697, 12 ), 43);  M_11 <= resize(x_pipe * to_signed( 11, 5 ), 36);  M_3635 <= resize(x_pipe * to_signed( 3635, 13 ), 44);   end if;   end if;   end process;   M_2816 <= shift_left(resize(M_11, 44), 8);    SummationChain : process (clk)   begin   if (clk'event and clk='1') then   if (nsi = '1') then   tap7_add641 <= resize("0",42) + resize(M_641,42);  tap6_add1697 <= resize(tap7_add641,44) + resize(M_1697,44);  tap5_add2816 <= resize(tap6_add1697,45) + resize(M_2816,45);  tap4_add3635 <= resize(tap5_add2816,46) + resize(M_3635,46);  tap3_add3635 <= resize(tap4_add3635,46) + resize(M_3635,46);  tap2_add2816 <= resize(tap3_add3635,46) + resize(M_2816,46);  tap1_add1697 <= resize(tap2_add2816,47) + resize(M_1697,47);  tap0_add641 <= resize(tap1_add1697,47) + resize(M_641,47);  y <= std_logic_vector(resize(tap0_add641,47));   end if;   end if;   end process;  end aFIR_Fxp1_GNRC;

[Altera_Forum]

The problem wont be in the VHDL. It will be with the pin assignments in the project file.

[Altera_Forum]

Hi, 

 Thanks for replying.  I'm just a VHDL beginner and actually having problem of "digesting" the codes. could you roughly explain the code ?  Regards, HJ.C

[Altera_Forum]

Theres a bunch of multipliers and adders.

[Altera_Forum]

You should start by reading some stuff on vhdl entity declarations, what ports are :rolleyes: . Then look for port maps for top level designs . You probably need a top module where you instantiate all your premade modules (audiocodec, filter ,...). In the top module you link your modules with port maps. If you don't know how a FIR filter somehow works, look it up?

[Altera_Forum]

--- Quote Start ---  Hi,  Thanks for replying.  I'm just a VHDL beginner and actually having problem of "digesting" the codes. could you roughly explain the code ?  Regards, HJ.C  --- Quote End ---    hii i want your help i have the same project as you -codec cyclone2 and FIR filter -you can tell some details about that!! email me in thank you:)