Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.

LTN
Novice
1,505 Views

Hi Intel,

When I am learning to use SFP+ interface of Cyclone 10 GX board, I designed the project with ATXPLL IP core、Reset Controller IP Core 、Cyclone 10 GX Transceiver Native PHY, and connected them like the user guide said:

LTN_0-1638433868216.png

Then I use Modelsim to simulate the whole project,but I can't check the "tx_serial_data"as expected,it's always 0. Then I find the "tx_clkout" and the "rx_clkout" are always 0 ,too.But I can't check the "tx_serial_clk0" signal.

Could you help me to check the problem? Did I use the IP Core in a wrong way?

Thanks.

0 Kudos
27 Replies
LTN
Novice
1,323 Views

Hi intel,

I didn't accept any reply up to now,I think maybe due to I didn't post the project. Now I  attach it.Could you help me?

Thank you very much,

Li

RichardTanSY_Intel
1,270 Views

Hi @LTN 

I’ve had a quick look art the design and I would perhaps change the source of the CLKUSR to be a general purpose CLK pin.

You should be able to observe the tx_serial_clk. Are you saying that it is 0, or are you saying that you cant see it at all? If it is 0, this suggests that perhaps the TX PLL is in reset. The same goes for the rx_clkout, if that is 0, then perhaps the PHY is in reset.

 

What are the status of all of the Reset Controller IP reset signals? Perhaps it would be easier if you showed me what the signals are doing.

 

The other obvious thing is that the CDR will not lock unless there is incoming data so you should of course ensure that your testbench implements a loopback between the tx_serial and rx_serial ports.

 

All things being good, I’d also ensure that you simulate for at least 20us.

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

LTN
Novice
1,252 Views

Hi @RichardTanSY_Intel ,

Thanks for your reply.

  1. First, about the CLKUSR,I haven't try this way up to now,but I will try as you said later.
  2. About the signals. I can't observe the tx_serial_clk , the reason is in the following post:Cyclone10GX:about ATX PLL IP Core.But in simulation I can observe the wave of pll_locked, and I will show it in attachment,I think this signal is working as I expected. So as the tx_clkout and the rx_clkout, I can observe them but they are all 0, I don't know why.
  3. About the Reset Controller IP reset signals, I can show you as following:reset_control.png

     

  4. About the loopback between the tx_serial and rx_serial ports.I accept your advise and connect the two signals together like this:LTN_1-1639300646570.png

    But due to the  previous problem, these signals are 0 all the time.

  5.  After simulating at least 20us,I get the result like this:>5000us>5000us

     

Regards,

Li.

 

RichardTanSY_Intel
1,235 Views

Hi @LTN 

The CDR needs toggling RX data in order for it to lock to data. For this to happen you of course need toggling data on the TX serial line (if running in loopback). Right now you don’t have toggling TX serial data because your tx_parallel_data is static 0. I need to understand why your TX_CLKOUT isn’t toggling though.

 

Can you please show the behaviour of the signals on the PHY IP and Reset Controller IP instead of the top level ports?

 

Regarding the tx_serial_clk,:Cyclone10GX:about ATX PLL IP Core. You need to consider that the fast transceiver signals do not go through the FPGA PLD fabric. So you cant use Signaltap because that is in the FPGA fabric. Simualtion is fine though because you can look anywhere.

 

Best Regards,

Richard Tan

LTN
Novice
1,229 Views

Hi @RichardTanSY_Intel ,

I don't understand what do you mean by"show the behaviour of the signals on the PHY IP and Reser Controller IP",do you mean the definition and function of them? If you mean this I can show you the user guide of these three IP Core-in one PDF which is downloaded from Intel:Intel Cyclone 10 GX Transceiver PHY User Guide, I hope this could help you find why TX_CLKOUT isn’t toggling.

By the way,this is the first I've heard of Signaltap, now I am going to learn to use it.

Thanks a lot,

Li.

 

RichardTanSY_Intel
1,213 Views

Hi @LTN 


I am not referring to the user guide.

Currently you are showing signals in the input and output ports of the top level. I’d like to see the actual behaviour of the signals on the PHY, TX PLL, and Reset Controller IP instances.

 

RichardTanSY_Intel
1,207 Views

Simulated one of the designs and saw the same behaviour that you describe. Could you try to enable the dynamic reconfiguration interface on the PHY, and ensure that the reconfig_clk is driven (same CLK as the Reset Controller should be OK), Please also ensure that the reconfig_reset input port gets a power on reset. When I did this it fixed my problem here.

LTN
Novice
1,200 Views

Hi @RichardTanSY_Intel ,

Could you send your fixed project to me for reference?

Thanks,

Li.

RichardTanSY_Intel
1,192 Views

Hi @LTN 

 

Here you go. 

LTN
Novice
1,181 Views

Hi @RichardTanSY_Intel ,

Thanks for your instant reply!

But after I did as you said--enable the dynamic reconfiguration interface on the PHY,a new problem has emerged: I can't simulate the problem by ModelSim now.

Is there any problem with my operation?

LTN_0-1639551527859.png

LTN_1-1639551569578.png

 

 

LTN
Novice
1,175 Views

Here is the modified project.

Regards,

Li.

RichardTanSY_Intel
1,108 Views

Hi @LTN 

 

You may checkout the post. Most likely you are missing a library in your simulation.  

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Arria-10-memory-simulation/td-p/217032

 

LTN
Novice
1,103 Views

Hi @RichardTanSY_Intel ,

Thanks very much for your reply, I find which lib is needed, and simulated the project successfully.This time i can show you the wave of reconfigurated Native PHY:

LTN_0-1640057825283.png

We can find that the wave of tx_clkout and rx_clkout is still wrong.What are the possible causes?


After reading the user guide(2.6.2 10GBASE-R),I think maybe the CGB of PHY isn't work(or maybe the PHY isn't work).The other question is that where do the there serial_clock sources come from?And how does the Clock Divider work?

LTN_1-1640058107906.png

 

Regards,

Li.

 

 

RichardTanSY_Intel
1,078 Views

Have you try to simulate the design example that was provided previously and compared it with yours? 

 

For other unique question, please kindly file a new case. This will helps with our case analysis that we use to assess our customer support requirements. Hope you understands. 

LTN
Novice
1,046 Views

Hi @RichardTanSY_Intel ,

I tried to simulate your example in QuartusPro 17.1,but I failed in the compile step.And I find the ip in that project maybe is generated by Pro 19.1? So I can't check it's parameter either.

Sorry,next time I will file a new post for the other questions.

Li.

LTN
Novice
985 Views

Hi @RichardTanSY_Intel ,

 I downloaded QuartusPro 19.1 and compared the example with mine, now i know what's the difference between them. In my project, i used the"10GBASE-R" preset of Native PHY IP Core, but the example didn't.Now i am trying to create another project like the example in verilog to simulate it.

By the way, Merry Christmas~

Best regards,

Li.

LTN
Novice
905 Views

Hi @RichardTanSY_Intel ,

I have downloaded Quartus Pro 19.1 and compared the example with my project.Then i modified its parameter like the example.But i didn't get what i want,only get this:

LTN_0-1640677201636.pngLTN_1-1640677228261.png

Do you know what's wrong with my project?

 

Thanks,

Li

RichardTanSY_Intel
849 Views

Hi @LTN 

 

May I know what is the current problem that you are facing? 

Could you help to share your whole design and the screenshot (with better resolution)? 

Somehow the screenshot attached in the forum is in low resolution so it does not help. 

 

Best Regards,

Richard Tan

 

LTN
Novice
773 Views

Hi @RichardTanSY_Intel ,

The problem I face are same as the beginning. Now I can check the tx_serial_clk0,it's working in 5156.25MHz.But the tx_clkout and the rx_clkout signal is still always '0'.I have been working on this for such a long time but there is still no solution.

I compared my project like the example you posted carefully,checked every link of PHY,reset control,andATX PLL.I am new to VHDL,maybe I didn't get the exact meaning of the example,which bothered me a lot.

Please help me...

Thanks very much.

Best Regards,

Li

RichardTanSY_Intel
743 Views

Hi @LTN 

in the previous reply I stated the following

 

“Simulated one of the designs and saw the same behaviour that you describe. Could you try to enable the dynamic reconfiguration interface on the PHY, and ensure that the reconfig_clk is driven (same CLK as the Reset Controller should be OK), Please also ensure that the reconfig_reset input port gets a power on reset. When I did this it fixed my problem here.”

 

The screenshots you provided do not show the Avalon Memory Mapped interface dynamic reconfiguration port clock or reset.

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