Cyclone10LP SEU CRC error implementation

[UF1]

Dear forum,

We have enabled the CRC_ERROR pin and we want to instantiate the block cyclone10lp_crcblock in order to retrieve the CRC calculated during configuration.

The cyclone10lp_crcblock is instantiated in a dedicated IP (attached with this message) where the CRC is output after 10s during 32 clocks.

When observed with signaltap there is no data output from the cyclone10lp_crcblock, could you help us to solve this issue ?

Regards,

GB

[Kshitij_Intel]

Hi GB,

CRC Calculation time is dependent on the device you are using, please refer below table mentioned in the link.

7.3.1.5. CRC Calculation Time (intel.com)

Also, for CRC_ERROR pin proper functionality, please go through the on board requirements mentioned in the below link.

7.3.1.1. CRC_ERROR Pin (intel.com)

Thank you,

Kshitij Goel

[UF1]

Hi K**bleep**ij,

I have already the documentation.

The issue is the CRC is never output from the cyclone10lp_crcblock.

Do you have any project example or any advice about the IP attached in the first mail ?

Also, we are waiting for the SEU license to validate the implementation with fault injection.

Regards,

Gorka

[Kshitij_Intel]

Hi Gorka,

For the CRC data output which is actually regout signal is the output of the error detection (i.e., the cyclone10lp_crcblock) shift register synchronized to the clk port to be read by the core logic. It shifts one bit at each cycle, so you should clock the clk signal 31 cycles to read out the 32 bits of the shift register.

Note: Any soft error failure affects the user logic. Therefore, do not rely on the regout signal in the 32-bit CRC signature to detect a soft error. The CRC_ERROR output signal provides a more accurate reading because is it not affected by a soft error.

Also, I do not see any attachments in the previous comments also.

For the SEU License, how you have registered/applied for it? Please contact in your regional FAE or sales representative. If not able to, please let me know the complete details then only I will be able to help it.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel

[UF1]

K**bleep**ij,

I already clock the cyclone10lp_crcblock but the output signal regout is stucked to 0 (I check it with signaltap).

As you don't see the attachment, here is the IP instantation and the process to clock out the data :

//----- Instantiation and configuration -------------------------------------------------------

uut_cyclone10lp_crcblock : cyclone10lp_crcblock
generic map
(
oscillator_divider => 8 ,
lpm_type => "cyclone10lp_crcblock"

)
Port map
(
clk          => s_clk_crcblock ,
shiftnld => s_shiftnld ,
ldsrc      => s_ldsrc ,
crcerror => s_crcerror ,
regout   => s_regout
);

s_shiftnld <= '0';
s_ldsrc <= '0';

s_clk_crcblock <= i_clk when s_output_crc='1' else '0';

o_regout <= s_regout;

o_error_pin <= s_crcerror;

//----- Process to output data  -------------------------------------------------------

pro_get_crc32: process(i_clk)
begin

if i_rst = '0' then

        sv_cnt <= (others=>'0');
        sv_crc32 <= (others=>'0');
       s_output_crc <= '0';

elsif rising_edge(i_clk) then

        -- Wait 10 s @ 60MHz then output register : 600000000
        if unsigned(sv_cnt) = 600000000 then
               s_output_crc <= '1';
                sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);

        -- Stop after 32 clocks 600000032
        elsif unsigned(sv_cnt) = 600000032 then
               s_output_crc <= '0';
               sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);

        -- Stop counter 33 clocks 600000033
        elsif unsigned(sv_cnt) = 600000033 then

        -- Count after reset
        else
               sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);
        end if;

        if s_output_crc = '1' then

               sv_crc32 <= sv_crc32(sv_crc32'length-2 downto 0) & s_regout;

        end if;

end if;
end process;

Regards,

Gorka BIROT

2.15.0.0