Cyclone3-Overshoot/Undershoot

[Altera_Forum]

Hi,

After PCB Design CIII – EP3C40 based board, in the post routing SI Simulation we are getting some overshoots and undershoots in DDR Signals and LVDS (As receiver) signals. As we are using DDR1 so all VCCIO pins of the banks dedicated for DDR along with the VCCIO pins of the banks dedicated LVDS are connected to 2.5V. In worst case we are getting the overshot/undershoot of 350mV near the FPGA pins i.e. at the FPGA pin we are getting 2.85V and -0.35V overshot and undershoot respectively.

In the Table 1–12 [Single-Ended I/O Standard Specifications] of Cyclone3 Handbook the Minimum value of VIL and Maximum value of VIH is given as -0.3 and VCCIO+0.3V respectively. Where as in Table 1–2Maximum Allowed Overshoot Voltage is defined as 3.95V for 100% and for under shoot it is said that it can go up to –2.0 V for input currents less than 100 mA and for periods shorter than 20 ns.

Can any one clarify if the VCCIO Pin is connected to 2.5V then up to what voltage level the Undershoot and Overshoot is permissible if the duration of these Overshoot/undershoot is less than 5nS.

In our board, we are using the FPGA as LVDS receiver only. So for SI Analysis we replaced the LVDS connector with 2nd Cyclone3 IBIS Model and used it as a LVDS Transmitter. In that case we are getting the overshoot/Undershoot of 600mV at the pins of Cyclone3 which is a LVDS receiver. Can any one clarify is this overshoot/Undershoot of 600mV is permissible?

In actual the LVDS signal is supposed to come from a 3.3V LVDS Transmitter. Where as, to use the Cyclone3 as LVDS receiver, the corresponding VCCIO is required to be connected to 2.5V. Please clarify whether this design is going to damage the Cyclone3 device?

Regards,

S. Sarkar

[Altera_Forum]

The RAM signals look quiet good, compared to some waveforms shown in Altera applications note. If they verify in real life, I would be happy. With terminated SSTL I/O standards you should mainly think about correct RAM operation rather than exceeding maximum ratings. 

 The LVDS waveforms may not endanger the CIII parts (most likely), but they show incorrect levels anyway. You seem to have forgotten the 100 ohm terminating resistors at the receiver. A correct lvDS signal has a much lower voltage variation, around a common mode level of about 1.2V. With termination resistors, the overshoot will be gone.

[Altera_Forum]

in 5 data signals of the ddr we are also getting cross talks above 150mv but it is within 200mv. can it be an issue in future? 

 Regarding the waveform of the LVDS signals, I also feel there was something wrong in the SI Simulation or in the IBIS model of the LVDS driver. Because the waveform we got using the IBIS model of 3.3v lvds transmitter ds90c3201 is much better and the voltage at the receiver pin is within 1.1V & 1.6V with the crossing point at 1.39V. But still the waveform shows some ringing for the differential termination of 100 Ohms.  i want you to comment on this waveform – whether there will be any issues because of these ringing? 

[Altera_Forum]

I would not expect problems from the crosstalk with DDR signals. The resisdual ringing with LVDS signals is also acceptable, although it could be most likely removed with better placement of termination resistor. But no problem at all.

[Altera_Forum]

Hello FvM, 

 Thanks for your comments on the waveforms. Because of space constraints we had to place the termination resistors a little far away from the FPGA. The average trace length between the Termination Resistor and the FPGA pin is approx 1000 mils. I am attaching the Gerber Files in PDF format in the forum. You are kindly requested to give a look and suggest any better solution if possible for the improvement of the signals.   Regards, S Sarkar 

[Altera_Forum]

Looks like you went a bit over the top with your trace length matching, but didn't control the trace spacing of your differential pairs so well. A small change here can create some nasty mismatches. 

 If I had to do terminators like this I'd be tempted to use 0402 surface mount resistors on the back of the BGA. You can make this work by shaving the corners off the pads (making them octagonal) and still have the pads fit in between the BGA ball breakout VIAs.