Cyclone4 JTAG issues

[Altera_Forum]

1.) We are using cyclone4 EP4CE55F23I7N on our custom board.(three FPGA’s per board as shown in schematic attached).It may be mentioned here that all the boards were working previously, but during development the JTAG interface on some boards is not working, but the FPGA seems to be working fine via passive serial mode.(also the same fpga u2’s jtag is going faulty in boards after some time. in one of the pcb the vccio and gnd of fpga u2 was showing shorted, on removing the bga and checking it was found that the device itself got faulty, which was earlier working fine). 

It is showing no device found when we try to connect JTAG via USB blaster.   On monitoring the difference between working and faulty board, it was found out that TMS or TCK pin on the FPGA side is remaining at logic LOW even when we try to connect JTAG via USB BLASTER.(even though it is pulled high as shown in schematic above.)  Also TMS or TCK pin of these faulty boards have very low resistance to ground as compared to working boards.  The working board’s JTAG interface goes faulty after some time during development.  our question is-what is the maximum current requirement of the vcca (jtag and analog section supply of fpga).and whether the usb blaster also draws power from our board regulator??  Also it was observed in one of the boards that the 2V5 regulator for JTAG supply has gone faulty.   since we are using a single 2.5v regulator with 0.8a to 0.9a current supplying capacity for our all three fpga’s jtag portion(as shown in schematic attached)on board, kindly suggest that will this be sufficient if we use jtag interface for full development and debugging functions like signal tap etc.??       also we read one blog on altera forum wherein similar problems were faced in jtag interface of the people using their custom development boards after working on the board for some time.(same is attached). kindly suggest what can be the issue??

[Altera_Forum]

Dear Rajesh 

 This types of problem generally comes due to power supply section. I suggest you to check power requirement of your FPGA. Your design will be reliable if you will use separate regulator for device connected to a Individual JTAG chain.   regards Nikhil