CycloneIVE LVDS Repeater

[Altera_Forum]

Hi Guys, 

I’m working at a Data Repeater based on LVDS channels.  I would like to use a Cyclone IVE (EP4CE15F17I7/ EP4CE22F17I7). The board receive a data flow by a 6 LVDS channel databus and re-transmit the data by a same type databus (using True Lvds channel of the CycloneE). Data will be transmitted/received with a 10bit serialization rate and 738Mbps datarate per channel, so the data clock is 73.48MHz. Repeaters will be connected by standard 60inch DVI Dual Link cable.  The question is: do you think is it possible to achieve the datarate specified.    Following the block diagram of the system and a simplified QuartusII Project.  https://www.alteraforum.com/forum/attachment.php?attachmentid=6877   Do you think there is something wrong? Do you have any hints to optimize the project?  If you compile the QuartusII project you will find a warning about PLL compensation, how can I solve this?  Warning (15055): PLL "LVDS_TX:inst2|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_lvds_tx:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input Info (15024): Input port INCLK[0] of node "LVDS_TX:inst2|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_lvds_tx:auto_generated|lvds_tx_pll" is driven by LVDS_Rx:inst1|altlvds_rx:ALTLVDS_RX_component|LVDS_Rx_lvds_rx:auto_generated|wire_lvds_rx_pll_clk[1]~clkctrl which is OUTCLK output port of Clock control block type node LVDS_Rx:inst1|altlvds_rx:ALTLVDS_RX_component|LVDS_Rx_lvds_rx:auto_generated|wire_lvds_rx_pll_clk[1]~clkctrl   Furthermore, I instantiate the ALT_LVDS_RX and ALT_LVDS_TX with internal an shared PLL but QuartusII instantiates 2 PLLs, why?     Thanks in advance

[Altera_Forum]

It's not clear where the LVDS clock should come from. Cyclone IV doesn't provide CDR (clock-data recovery) for LVDS receivers.

[Altera_Forum]

Thanks for your attention. 

 Repeater board are connected in daisy chain. Each Repeater Board receive the clock (and data) from the ALT_LVDS_TX IP of the previous board and retransmit clock (and data) to the next one.  Obvoiously the first board in the the daisy chain doesn't receive clock and data from the ALT_LVDS_TX IP of the previous board but generate both internally (actually receive them from a video converter) and transmit them to the second board and so on.  Hope it's more clear now.