D flip-flop latches FPGA input pin's signal wrong!

[Altera_Forum]

Hello everyone: Why D flip-flop latches signal which comes from the FPGA input pin will go wrong and how to avoid it? 

when deal with the externally input RGB signal deriving form a LCD driver, there is something wrong that some part of the image drift. We detected the error by comparing the OK data generated internally with the input data externally ,that goes like bellow:   there are some codes in verilog HDL source code: reg DE_r, DE_rr; always @ (negedge In_LCD_CLK) begin DE_r <= In_LCD_DE; DE_rr <= DE_r; end    The frequency of signal In_LCD_CLK is just only 6.5M which is not high. and the data latched on the falling edge of In_LCD_CLK. We use this synchronized clock In_LCD_CLK to latch In_LCD_DE with two D_ff, and the RTL view goes like bellow: https://www.alteraforum.com/forum/attachment.php?attachmentid=8242  we are using 100M sigtab II sample clock to analysis the waveform ,and most of the time the waveform is OK: https://www.alteraforum.com/forum/attachment.php?attachmentid=8243  Just as our understanding of the D_ff, the output Q is only a single edge (here is falling) change,and in other moments, the value remains unchanged. But when the error occurred: https://www.alteraforum.com/forum/attachment.php?attachmentid=8244  This phenomenon is really strange and serious challenge our nous and knowledge structure.   As we all know, D flip-flop is a only single edge transition (here is In_LCD_CLK’s falling edge ) when it is sampling latch data, while at the other edge of the output value is held constant.   This error has not relation with the hardware,because the sigtabII could sample the error! In fact Later I was using the 100M sampling clock to avoid this problem and obtain the correct data without using the synchronized clock In_LCD_CLK . If the quality of In_LCD_CLK is not good ,but I used 100M clock sampling In_LCD_CLK falling edge then get a very stable and satisfactory image! So, I am very doubt about this phenomenon!

[Altera_Forum]

your signal In_LCD_DE is from different clock domain (i.e.not synchronised to this clock) and so correctly you have use two stage synchroniser. You must expect this behavior and do not sample until second flip. So in principle don't worry about signaltap result. However you got a problem reported so I assume some other clocks are involved and we need better picture of your design.