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Altera_Forum
Honored Contributor I
750 Views

D flip flop trouble

Hello... 

I've written a simple VERILOG flip flop code set that isn't working in hardware. 

 

I have a debounced switch input called SW3_2. Upon the POSEDGE the output SW3_2_PRESS should toggle state. I've run this on the simulator and it works perfectly there but when it's burned into the CPLD I may have to push the button several times before it will toggle. I've verified the input waveform is clean and sharp. I think there may be a timing problem internally as this is unclocked. Incidental to this is a 2:1 MUX. Please focus on the last block. 

 

 

module StuMicController  

(SW1_1,SW1_2,SW2_1,SW2_2,SW3_1,SW3_2,SW1_LATCH,SW2_LATCH,SW3_LATCH,SW1_1_PRESS,SW1_1_RLS,SW1_2_PRESS,SW1_2_RLS,SW2_1_PRESS, 

SW2_1_RLS,SW2_2_PRESS,SW2_2_RLS,SW3_1_PRESS,SW3_1_RLS,SW3_2_PRESS,SW3_2_RLS, 

TALK1_LED,MUTE1_LED,TALK2_LED,MUTE2_LED,TALK3_LED,MUTE3_LED,PIN44,PIN43,PIN2); 

//INPUT PINS: Switch contacts and latch-enable jumpers 

input SW1_1; 

input SW1_2; 

input SW2_1; 

input SW2_2; 

input SW3_1; 

input SW3_2; 

input SW1_LATCH; 

input SW2_LATCH; 

input SW3_LATCH; 

input PIN44; 

input PIN43; 

input PIN2; 

//OUTPUT PINS: Switch pressed(1/2), switch released(1/2), LED (1/2) 

output SW1_1_PRESS; 

output SW1_1_RLS; 

output SW1_2_PRESS; 

output SW1_2_RLS; 

output SW2_1_PRESS; 

output SW2_1_RLS; 

output SW2_2_PRESS; 

output SW2_2_RLS; 

output SW3_1_PRESS; 

output SW3_1_RLS; 

output SW3_2_PRESS; 

output SW3_2_RLS; 

output TALK1_LED; 

output MUTE1_LED; 

output TALK2_LED; 

output MUTE2_LED; 

output TALK3_LED; 

output MUTE3_LED; 

reg q1; 

reg q2; 

reg q3; 

initial q1 = 1'b1; 

initial q2 = 1'b1; 

initial q3 = 1'b1; 

 

 

 

//Define FLIP FLOP Logic Here 

always@(posedge SW1_2) //SWITCH 1 D-flipflop 

begin 

q1 <= ~q1; 

end  

assign SW1_2_PRESS = ~SW1_LATCH? q1:~SW1_2; //Build 2:1 MUX (mode switch) 

assign SW1_1_PRESS = ~SW1_1; 

assign SW1_2_RLS = ~SW1_2_PRESS; 

assign SW1_1_RLS = ~SW1_1_PRESS; 

assign MUTE1_LED = ~SW1_2_PRESS; 

assign TALK1_LED = SW1_1; 

 

 

always@(posedge SW2_2) //SWITCH 2 D-flipflop 

begin 

q2 <= ~q2;  

end  

assign SW2_2_PRESS = ~SW2_LATCH? q2:~SW2_2; //Build 2:1 MUX (mode switch) 

assign SW2_1_PRESS = ~SW2_1; 

assign SW2_2_RLS = ~SW2_2_PRESS; 

assign SW2_1_RLS = ~SW2_1_PRESS; 

assign MUTE2_LED = ~SW2_2_PRESS; 

assign TALK2_LED = SW2_1; 

 

 

always@(posedge SW3_2) //SWITCH 3 D-flipflop 

begin  

q3 <= ~q3;  

end  

 

assign mux3 = ~SW3_LATCH? q3:~SW3_2; //Build 2:1 MUX (mode switch) 

assign SW3_1_PRESS = ~SW3_1; 

assign SW3_2_PRESS = mux3; 

assign SW3_2_RLS = ~mux3; 

assign SW3_1_RLS = ~SW3_1; 

assign MUTE3_LED = ~mux3; 

assign TALK3_LED = SW3_1; 

 

 

endmodule
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2 Replies
Altera_Forum
Honored Contributor I
60 Views

The sim may have worked fine since you initialized the registers to 1. Registers initialize to 0 in hardware. 

 

A circuit like this should really be clocked. Here's one I like that I've been using that uses a counter. button_qual high indicates a debounced button press: 

 

module button_debounce( 

input wire clock, 

input wire button, 

output reg button_qual = 1'b0 

); 

 

reg [19:0] button_count = 20'h00000; 

reg [2:0] button_reg = 3'b000; 

reg [1:0] button_state = 2'b00; 

 

always @ (posedge clock) 

begin 

button_reg <= {button_reg[1:0],button}; 

case (button_state) 

2'b00: begin 

button_qual <= 1'b0; 

button_count <= 8'h00; 

if (button_reg[2]) 

button_state <= 2'b01; 

else 

button_state <= 2'b00; 

end 

2'b01: begin 

button_qual <= 1'b1; 

button_count <= button_count + 1'b1; 

button_state <= 2'b10; 

end 

2'b10: begin 

button_qual <= 1'b1; 

button_count <= button_count + 1'b1; 

button_state <= button_count[4] ? 2'b11 : 2'b10; 

end 

2'b11: begin 

button_qual <= 1'b0; 

button_count <= button_count + 1'b1; 

button_state <= button_count[19] ? 2'b00 : 2'b11; 

end 

endcase 

end 

 

endmodule
Altera_Forum
Honored Contributor I
60 Views

Thank you for that. I have an external hardware based debounce circuit so that's not an issue. I did find something interesting though. The CPLD reset pin had been brought out as if it were a general input pin and the circuitry it was connected to was holding it in perpetual reset. That would explain why the registers wouldn't release. I'm going to break that line and add a reset chip and try again later this week.

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