DCFIFO read/write request control

[Altera_Forum]

Hi, 

 I'm using dcfifo's in a design with the rdreq and wrreq signals. The clock on both sides of the fifo is the same frequency but it will be out of phase. When the fifo comes out of reset, should I be delaying the rdreq signal with respect to the wreq signal to ensure that that an attempt is not made to read from an empty fifo or does this not matter? I have enabled both underflow and overflow protection. Under normal operation I just want them tied high as I just want it to do some phase compensation.  Regards  MT

[Altera_Forum]

Hi, 

 Altera always warns of such attempts. I will make sure that I got data on the read side before I read else things become unpredictable according to altera... I am not sure if underflow protection will just stop that.  additionally, for dcfifo, it is safer to release reset synchronised to write clock.  kaz

[Altera_Forum]

Thanks Kaz. 

 I've been using signal tap to look at the fifo flags on both sides to see what's happening. I presume as soon as rdempty goes low (assuming when it's high, nothing has been written), I can start to read. From here on, I suppose I can keep the rdrq/wreq lines tied high?  I know when you build the fifo, there is an option that asks if you want to sync aclr to wrclk. I've kept this disabled becaue I use some regs to sync the reset to wrclk. With this option on, I had problems.