DDR PIN placement error

[Altera_Forum]

Hi all, 

 I use a Cyclone IV E EP4CE40F23C8 with Quartus 11.0    I have this error message when i try to place ddr pins     --- Quote Start ---   Error: altmemphy pin placement was unsuccessful Error: The assigned location PIN U15 for DQS pin "mem_dqs[0]" is not a legal location Info: PIN C2 is a legal pin location Info: PIN C8 is a legal pin location Error: The assigned location PIN AA5 for DQ pin "mem_dq[0]" is not a legal location Info: There is no legal DQ location that supports 9 DQ pins Error: The assigned location PIN AB5 for DQ pin "mem_dq[1]" is not a legal location Info: There is no legal DQ location that supports 9 DQ pins Error: The assigned location PIN W6 for DQ pin "mem_dq[2]" is not a legal location   ....   --- Quote End ---       you can find my sdc file (attachment)   Thanks for your help :)

[Altera_Forum]

the error message is pretty helpful in this case. for example, pin U15 is not a legal placement for a DQS pin, or even a DQ pin. you should open the pin planner and take a look at the S pins to know where the legal DQS pins are, and Q for the legal DQ pin locations 

 you may need to rework your pin out to allow for compatible VCCIO on your DDR banks

[Altera_Forum]

Thank you, 

 but how i rework my pin, it depends on the hardware? i can not choose other pins

[Altera_Forum]

i think you're out of luck and will need a board spin

[Altera_Forum]

It also happened to me. During layout we inadvertently made a few wrong swappings ... 

Now the Cyclone IV manual states that the DQS are not used for capture, as there is no DLL circuitry on-board. The ALT-MemPHY uses a dedicated capture clock (that one it phase-shifts to make up for PVT-variations).  I didn't see any special silicon for the DQS/DQ/DM pins, so in theory any IO pin should be able to serve the purpose. Is there a document that reveals the DQ/DQS/DM mysteries, why they are fixed to these 'exact' locations ?

[Altera_Forum]

--- Quote Start ---   Is there a document that reveals the DQ/DQS/DM mysteries   --- Quote End ---  The Cyclone IV pinout files are here:  http://www.altera.com/literature/lit-dp.jsp?category=cyc%204&showspreadsheet=y  They list the DQS etc.  When comparing parts, I use the text version of these files and write Tcl scripts to parse the files.    --- Quote Start ---    why they are fixed to these 'exact' locations ?  --- Quote End ---  DDR2/3 interfacing requires phase shifting the strobe clock to capture the data. Hence a DQS is grouped with a block of DQ registers.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

   --- Quote Start ---  DDR2/3 interfacing requires phase shifting the strobe clock to capture the data.  --- Quote End ---   In Cyclone IV the DQS is not used to capture the DDR2 data. This is stated several times in the Cyclone IV data-sheet. Instead ALT-MemPHY uses a phase-shifted clock from the PLL (that generates all memory clocks) to capture the data. It looks to me that all (most) IO-pins are created equal (DDR-out an OE registers etc. in the IO-cell, DDR-in registers in the logic fabric) so how come the DQ/DQS/DQM-pins are more equal? That is the mystery I'd like to see revealed.  Regards,  Josy

[Altera_Forum]

thank you guys, 

 I will request a new board spin to hw team :s   Another question : have you any recommendation for flash memory pinout?   I use Spansion S29GL512N it dosen't work also :( (you can find the project archive to test flash here)

[Altera_Forum]

Hi Josy, 

   --- Quote Start ---   In Cyclone IV the DQS is not used to capture the DDR2 data. This is stated several times in the Cyclone IV data-sheet. Instead ALT-MemPHY uses a phase-shifted clock from the PLL (that generates all memory clocks) to capture the data.   --- Quote End ---  Thanks for clarifying that. I am using the Stratix IV devices, and incorrectly assumed the interface was the same on the Cyclone IV devices. I'd had to use the Stratix IV pin assignment tables to try to figure out the assignments for DDR and QDR on the Stratix IV GX Development kit.    --- Quote Start ---    It looks to me that all (most) IO-pins are created equal (DDR-out an OE registers etc. in the IO-cell, DDR-in registers in the logic fabric) so how come the DQ/DQS/DQM-pins are more equal? That is the mystery I'd like to see revealed.   --- Quote End ---  An interesting mystery indeed. Write a DDR2 interface independently of the Altera IP?  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   Another question : have you any recommendation for flash memory pinout?   I use Spansion S29GL512N it dosen't work also :( (you can find the project archive to test flash here)  --- Quote End ---    The flash interface can use any compatible I/O pins.  Did you simulate your design with the Spansion flash model, or at least simulate it with a simple memory model and check that you have the read/write timing correct?  I've used the Spansion flash on many boards, without issues. Eg., see the timing on p30  http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf   Cheers, Dave

[Altera_Forum]

Hi Dave, 

   --- Quote Start ---  I am using the Stratix IV devices  --- Quote End ---   In the more commercial projects we have to do with Cyclone IV and if possible the smaller (cheaper) ones, my customer keeps repeating almost daily ...    --- Quote Start ---  Write a DDR2 interface independently of the Altera IP?  --- Quote End ---   I'm doing exactly that, as a midnight project though. And I must confess, playing it safe, I stuck to the 'Altera assigned DQS/DQ/DM pins' while developing my PHY. But as I said we swapped a few pins incorrectly and in this project I was going to use the Altera IP (until I got my PHY and Controller tuned) to get the system off the ground. Now my partner-developer is complaining that he has to run a NIOSII Ethernet stack with just the internal memory ... My Phy and controller are quite small compared to the Altera IP, and are dedicated to driving a single memory chip ( or at maximum a single rank Dimm) only and is targeted at Cyclone devices. (Although the idea should also work for Stratix devices ...) I'll compare a compilation with some non DQS-DQ pins to the compilation with 'correctly assigned' pins.  Regards,  Josy

[Altera_Forum]

Hi Josy, 

   --- Quote Start ---   I'm doing exactly that, as a midnight project though. And I must confess, playing it safe, I stuck to the 'Altera assigned DQS/DQ/DM pins' while developing my PHY. But as I said we swapped a few pins incorrectly and in this project I was going to use the Altera IP (until I got my PHY and Controller tuned) to get the system off the ground. Now my partner-developer is complaining that he has to run a NIOSII Ethernet stack with just the internal memory ... My Phy and controller are quite small compared to the Altera IP, and are dedicated to driving a single memory chip ( or at maximum a single rank Dimm) only and is targeted at Cyclone devices. (Although the idea should also work for Stratix devices ...) I'll compare a compilation with some non DQS-DQ pins to the compilation with 'correctly assigned' pins.   --- Quote End ---  I was planning on taking a crack at writing an IP core for the low-power DDR on the BeMicro-SDK kit. I've written an SDRAM controller before so figured it wouldn't be too impossible (famous last words ...).  Are you writing your core in Verilog or VHDL? Are you simulating using Modelsim and some Micron memory modules? Any chance you'll share your code, or at least your experiences once you get things working?  Cheers, Dave

[Altera_Forum]

Hi Dave, 

   --- Quote Start ---  I've written an SDRAM controller before so figured it wouldn't be too impossible (famous last words ...).  --- Quote End ---   I too progressed via that route. If you keep the controller simple, staying away from the fancy things Altera implements in their HPC II controller, it isn't that complex. And in the end the simple controller outperforms the complex one (time and again).   --- Quote Start ---  Are you writing your core in Verilog or VHDL?  --- Quote End ---   It is in VHDL (I try not to touch Veriog -> see http://www.alteraforum.com/forum/showthread.php?t=30879 (http://www.alteraforum.com/forum/showthread.php?t=30879))   --- Quote Start ---  Are you simulating using Modelsim and some Micron memory modules?  --- Quote End ---   I'm an old-time AHDL hand and I'm hooked on the internal Quartus II simulator and procrastinating on ModelSim , you will tell me I'm wrong, of course :).   --- Quote Start ---  Any chance you'll share your code, or at least your experiences once you get things working?  --- Quote End ---   I was contemplating to share it when it was ready (just to show off) but I guess sharing with you would probably get me on the way to ModelSim (even advanced: with models!)  Best regards,  Josy

[Altera_Forum]

Hi Josy, 

   --- Quote Start ---   If you keep the controller simple, staying away from the fancy things Altera implements in their HPC II controller, it isn't that complex. And in the end the simple controller outperforms the complex one (time and again).   --- Quote End ---  I like simple too :)    --- Quote Start ---    It is in VHDL   --- Quote End ---  Great!    --- Quote Start ---    I'm an old-time AHDL hand and I'm hooked on the internal Quartus II simulator and procrastinating on ModelSim , you will tell me I'm wrong, of course :).  I was contemplating to share it when it was ready (just to show off) but I guess sharing with you would probably get me on the way to ModelSim (even advanced: with models!)   --- Quote End ---  I'd be happy to create a Modelsim testbench around it. Hey, I'll even throw in a VHDL based Avalon-MM master bus functional model for good measure.  Send me an email off-list when your hardware tests show your controller is working, and I'll take it for a spin in the simulator, and see if it'll work with the LPDDR on the BeMicro-SDK. We can post the final version once its working.  Cheers, Dave

[Altera_Forum]

Thank you Dave, 

 I return to the main problem THE DDR :s I have 2 BANK (3 & 4) exclusively for DDR (2.5v), team hw ask me the placement made by Quartus if i select only the bank 3 and 4.   result i have only some critical warning...     --- Quote Start ---   Warning: Unable to place CK/CKn pair mem_clk and mem_clk_n on a differential pin pair because mem_clk has been assigned to a non-differential pin   --- Quote End ---       --- Quote Start ---   Critical Warning: Memory clock pins mem_clk and mem_clk_n must be placed on DIFFIO p- and n-pins   --- Quote End ---     when i chek pin planner:  mem_clk : Y6  mem_clk_n : T10    --- Quote Start ---   Critical Warning: ALTMEMPHY IP was generated using a speedgrade of 6, but is being compiled for a speedgrade of 8. Timing analysis may not be valid due to violated timing model assumptions.   --- Quote End ---  

[Altera_Forum]

--- Quote Start ---   result i have only some critical warning...   --- Quote End ---    The warnings are telling you what you have done wrong. Consult the pin function tables I posted the link to earlier, and it will tell you what the corresponding differential pair groupings are. The Quartus pin planner device view also shows the pairing.  The warning about device speed grade probably means that the DDR controller was not created with the 'project default device', just go back and regenerate the core.  Cheers, Dave

[Altera_Forum]

Yes but even when i choose only placement for "mem_clk" in DIFFIO_p T8 and  

"mem_clk_n" in DIFFIO_n T9 (quartus default placement for DQ, DQS, DM...) i have the same result   when i chek pin planner:  mem_clk : Y6  mem_clk_n : T10

[Altera_Forum]

--- Quote Start ---  Yes but even when i choose only placement for "mem_clk" in DIFFIO_p T8 and  "mem_clk_n" in DIFFIO_n T9 (quartus default placement for DQ, DQS, DM...) i have the same result   when i chek pin planner:  mem_clk : Y6  mem_clk_n : T10  --- Quote End ---    It sounds like you did not change the assignments.  When you are in Pin Planner, double-click on the cell that says PIN_Y6, and edit it to change it to PIN_T8. Then change PIN_T10 to PIN_T9. Click save, and place-and-route your design.  Cheers, Dave

[Altera_Forum]

Thank you Dave, 

 I have the some problem :s Please find attached project