DDR on Cyclone V Interfacing to LTC2107 ADC, 200 MHz and Half-rate Hard Fifo

[Altera_Forum]

Hello!  

 I was hoping for some advice using the DDR interface on a Cyclone 5 SoC.   First the Setup:  Enclustra SA1 SOM (with a Cyclone V SX part) on an Enclustra Mercury+ PE1000 base card and a Linear FMC module hosting the LTC2107 ADC. The Base card is clocking the ADC at 200 MHz. I use the ClockOut pin of the ADC to time the data coming out.   I get everything working somewhat OK with the exception of the flyer codes (see attachment). This indicates timing errors and sure enough  TimeQuest tells me that every data output from my ALTDDIO_IN instantiation is a failed path.   I did some digging into the IO structure for a Cyclone V and found that the input data path for DDR goes through a hard read fifo that has the  capacity to halve the data rate. The ALTDDIO_IN IP does not have the setting to do this. The only IP I found that exposes the hard read fifo is the  ALTDQ_DQS2 IP. However, when I go to instantiate it, I get fitter errors. I'm guessing its because neither the input clock from the ADC nor any  of the LVDS data lines are grouped into a DQS group. The input clock however is connected to a global clock.   So my questions are:  Is it possible to configure the ALTDQ_DQS IP to simply allow me to use the DDR and and Fifo portions at half the data rate?  If not, how might I go about solving the timing errors ?   Thanks!