- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Have you had a look through this document: http://www.altera.com/literature/hb/external-memory/emi_altmemphy_ref_debug_toolkit.pdf Lots of useful suggestions there. When I had a similar problem I built a stripped down design around the example design produced by the DDR2 megafunction and turned on the debug. Included the JTAG interface and then I could see at what stage it fell over during PHY initialization and calibration. Very useful. Is the board custom or one of the development kits. If custom, are you sure you have a termination correct? Mark.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Mark,
I am looking into the documentation. My board's RAM design is similar to Altera's Cyclone iv development Kit. Regards, Iyan
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page