Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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DDR2 interface problem

Altera_Forum
Honored Contributor II
‎11-20-2007 05:27 PM
1,118 Views

When I tried to fit my design into Cycleon II, I got an error message 

Error: DQS I/O pin "ddr2_dqs[1]" does not feed a Clock Delay Control block 

 

I use Altera's DDR2 controller, why does this happen? Do I need put a "altdqs" megafunction between the DQS output of the DDR2 Controller and the DQS pin on FPGA?
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Altera_Forum
Honored Contributor II
‎03-06-2008 11:09 AM
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I've the same problem. Do you know the solution?

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