Hello,
I'm working on a design that is going to use a Arria II FPGA (EP2AGX125EF35C6) , SDI, and two DDR2 chips. In my current quartus ii project, including two main altera IP core, that is SDI triple-stantard receiver and DDR2 controller(half-rate, 300M). My problem is as follows.
1. When compilation finished, there exist three critical warnings on DDR2’s read capture time. That is, DDR2 timing is violated. Is this have Negative impact on other logic’s function?
2. Besides, when debugging with signaltap II, the logic work well. However, when compile with no signaltap II, download the sof into FPGA, the logic function have critical problems, I don’t know whether this problem caused by DDR2’s violated timing?
I will appreciate your guidance with this issue.
Best regards, thanks.
