Hi all,
I am trying to write to a DDR3 memory slave using an avalon interface (Cyclone V GT dev kit). I am using the avalon burst master templates provided by Altera (
https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html). I am continually writing the data in a loop using the write burst master. However, after few complete transfers, the wait request signal from the slave stays high in the middle of a transfer and the transfer stalls indefinitely. I have tapped to the length variable from the master template and I can infer that the write stalls in the middle of a transfer due to the wait request signal.
Can anyone advise me why this behaviour, please?
Kind regards,
Lijo
