Hi,
Im using a DDR3 controller based on uniphy and using altera developpement kit, with the following configuration:
- Data width = 64bits.
- Memory data bus width = 16bits.
- Burst type: BC4/BL8 (on-the-fly).
- PHY interface= UNIPHY
When i run the controller on target, i get the following problem :cry::
The controller performs a write access of the words "data1" and "data2" in BL8 mode, starting from the column 0x0004 (addresses observed at the AFI interface).
After performing read accesses, the data is stored as follow:
- data1 is stored at column 0x0000 instead of 0x0004.
- data2 is stored at column 0x0004 instead of 0x0008.
When i do the same test but with starting address column 0x0000 or olumn 0x0008, the data is read correctly (i.e. no addresses changing).
This problems doesn't appear when i run the virtual simulation using a memory model, but i happens only when i perform the test on the board :confused:.
Is there something special about the BL8 burst?
It appears to me that the BL8 burst is allowed only if the column address is multiple of 8 (i.e. column 0x0004 and column 0x000C can't be accessed in BL8); is this correct?
Thank you very much for your help.
Best regards.
:)
