DDR3 Layout Length Matching

[Altera_Forum]

Hello, 

 I am laying out a DDR3 memory based on 4x 16bit chips and have seen in EMI Handbook Vol 2, Chap 4, Table 4-23 that "data, address and command signals must have matched length traces to within +/-250mil". However my understanding is that each Byte Lane Group (DQ, DQS & DM) must be matched within itself, but does not have to match the Address/Command Group.   - TMS320DM8148 manual   "It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is only required within each byte."  - iMX53 user guide   Address/Command: Min = Clk-200mil, Max = Clk.   Byte Lane Groups: Min = 0, Max = Clk.  So, for example all Byte Lanes could be around 1" (but matched to <50 mil within each lane), and Address/Command around 2" (matched to <50mil within group).  Is my understanding correct?  Thanks, Ken

[Altera_Forum]

You are quoting Table 4-23, ddr2 SDRAM Layout Guidelines.

[Altera_Forum]

Yes, but it states that "These layout guidelines also apply to DDR3 SDRAM without leveling interfaces". 

 Thanks, Ken

[Altera_Forum]

Hi ken, 

I want to make my first layout with iMX53 and 4 DDR3, haveyou resolved your thread named "DDR3 Layout Length Matching"of november 26th, 2012, 11:06 PM? In MX53UG.pdf table2-1 and table 2-2 isn'tin accordance to table 2-4 can you help me please? Thanks. Laurent 

[Altera_Forum]

Hi Laurent, 

 Yes, my original assumption was correct. The clock could have been 2" and the byte groups 1", but I did end up with them being the same at approx 2".  Your question: "In MX53UG.pdf table2-1 and table 2-2 isn'tin accordance to table 2-4 can you help me please?"  In table 2.4 it looks like they have used the guide form table 2.2 'routing by byte groups', as the byte groups are around 614mil, and the clock is 1175mil. This meets the requirement Byte Group max < Clock min. However note that in table 2.2 the requirement is that all byte groups are matched from group to group by 50mil, so the easiest thing is to make a lenght matching requirement for D0..31 of 25mil across the whole bank, which is what it looks like they have done (all D, DQM, DQS are within a few mil).  For the FPGA design I was working on (4 chips 64 bit) I ended up with all byte group lenghts equal within each 32 bit bank.  Although I did need to compensate for different lenghts on internal/external layers, as some byte groups were on external layers.  [signal propogation is approx 15-20% faster on external layers due to lower dielectric as trace is in 'air'] If you keep all byte groups on internal layers, then this should not be needed, but note that if the clock is external then it should be at least 20% longer. This is the case in teble 2.4 (clock is 90% longer), and fig 2.22 (clock is external).  For a very useful video on how it's done in Altium, see: http://www.fedevel.com/welldoneblog/2011/07/altium-designer-ddr3-routing-and-pcb-layout-video/  Hope this helps, Ken

[Altera_Forum]

Hi Ken, 

Thank you very much I understand better. You say," if clock is external then it should be at least 20% longer. This is the case in teble 2.4 (clock is 90% longer), and fig 2.22 (clock is external)." For exemple if clock is in TOP and other in internal layer , this length must be +20% mini and +90%max. It's goodt?  In MX53GU.pdf table 2-2, on line 2 "Address and Command" and line 7 "Control signals". The length recommended is between Clock (min) – 200 and Clock (min). But nothing is specified about address, command and control signals in the table 2-4. What are their lengths in table 2-4?   Thank. Laurent

[Altera_Forum]

Hi Laurent, 

I think you have a misunderstanding of table 2.4. It is not a specification, only an example of their design, and they don't show the address/command lines. 90% is what I saw in their example (1175 / 614 = 1.9). It's not a spec!  For the spec you should follow table 2.2, which as you say, shows the address & command as between clock-200 and clock.

[Altera_Forum]

Hi Ken, 

I make difference beteween specification and and example,it's good. I want make layout with iMX53 and 4 DDR3, like chapter 2.5.11 Gbyte Topologies. Now, I think I understood matching but, I see that addressis more long (about +150mil) than clock in layout of evaluation board IMX53-start-R(it's also 1Gbyte topologies). There's a reason? Laurent

[Altera_Forum]

--- Quote Start ---  Hi Ken, I make difference beteween specification and and example,it's good. I want make layout with iMX53 and 4 DDR3, like chapter 2.5.11 Gbyte Topologies. Now, I think I understood matching but, I see that addressis more long (about +150mil) than clock in layout of evaluation board IMX53-start-R(it's also 1Gbyte topologies). There's a reason? Laurent  --- Quote End ---    Hi Laurent, I don't have the layout you're referring to, so perhaps it would be better to ask in an iMX53 forum. If it's a working layout then you could always copy it. Good luck with your design!

[Altera_Forum]

Hi Ken, 

Ok, I don't have answer in iMX53 forum, Thank you for your clarification.