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DDR3 UniPHY problems

Altera_Forum
Honored Contributor II
‎09-19-2013 11:12 AM
1,354 Views

Hello, 

 

I am trying to incude a DDR3 UniPHY Controller megacore to my design, but I am experiencing several issues. I am working on a TR4 development kit (TERASIC) based on the STRATIX IV FPGA (EP4SGX530KH40C2). 

Basically I have generated the Megacore by using the Megawizard plug-in manager, I have parametrized my DDR3 block and I have generated the entity for my design. 

After this I have normally instantiated the DDR3_Controller by defining it as a component inside my VHDL code, and I have connected it to the right signals. In addition I have mapped them to the pins on my development board by using the pin planner. 

 

I haven´t still developed a control logic to drive the controller but this shouldn´t be a problem. 

 

When I try to compile my design, it already fails in the Analysis and Synthesis step, and I get the following errors: 

 

Error (15700): Termination calibration block atom "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|altera_mem_if_oct_stratixiv:oct0|sd1a_0" uses RUP port, which must be connected to an I/O atom in input mode Error (15700): Termination calibration block atom "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|altera_mem_if_oct_stratixiv:oct0|sd1a_0" uses RUP port, which must be connected to a dedicated I/O atom with no other fanout Error (15700): Termination calibration block atom "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|altera_mem_if_oct_stratixiv:oct0|sd1a_0" uses RDN port, which must be connected to an I/O atom in input mode Error (15700): Termination calibration block atom "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|altera_mem_if_oct_stratixiv:oct0|sd1a_0" uses RDN port, which must be connected to a dedicated I/O atom with no other fanout Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15853): Input port IBAR of I/O input buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|strobe_in" must be driven by a top-level pin Error (15065): Clock input port inclk of PLL "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_pll0:pll0|altpll:upll_memphy|altpll_8nd3:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Info (15024): Input port INCLK of node "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_pll0:pll0|altpll:upll_memphy|altpll_8nd3:auto_generated|pll1" is not connected Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin Error (15856): Output port O of I/O output buffer "SDRAM_Controller:b7|SDRAM_Controller_0002:sdram_controller_inst|SDRAM_Controller_p0:p0|SDRAM_Controller_p0_memphy:umemphy|SDRAM_Controller_p0_new_io_pads:uio_pads|SDRAM_Controller_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|obuf_os_bar_0" must drive a top-level pin 

 

What is the problem here? How can I fix this? 

I am getting problems both by compiling the examples automatically generated by the Megacore, and the examples developed with my board are quite bugged and fully not working... 

 

BR,  

Giovanni.
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Altera_Forum
Honored Contributor II
‎12-12-2013 09:55 AM
528 Views

Hi Giovanni, 

 

you have to launch a .tcl script to complete the constraint file 

for the DDR3 pins. It is something like <your_controller_name>_p0_pin_assignments.tcl 

 

hope this could solve your problem, 

 

regards,
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