Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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DDR4 can not be read

mark_lee
New Contributor I
210 Views

hi team  

     There are an ddr4_ctrl modular in my design, I add it in the qsys ,  connect  it  to two modular by avalon Bus. One is the PCIE ,  the other is my  application modular (APP) .   run Qsys to Genarat HDL . a "mm_interconnect_3 " modular will be generated.  As below show:

DDR4_3.jpg

 I run the design in my  board ,  PCIE can read and write the DDR4 chip ,  but my  application modular can not read and write the DDR4 chip .  single Tap  get the "nano_adrv9009_0_m1_waitrequest"  keep " high" .  

    waht is the problem 

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3 Replies
AdzimZM_Intel
Employee
185 Views

Hi Mark,


May I know how do you perform this R/W operation?


I just curious where are all this components come from, is it from Intel IP?


Just for sanity check, is there any connectivity issue between the PCIE modular and APP modular?


Is your design are working as expected in the simulation?


Regards,

Adzim


AdzimZM_Intel
Employee
117 Views

Hi Mark,


Do you have any update on this thread?


Regards,

Adzim


AdzimZM_Intel
Employee
101 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.



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