There are an ddr4_ctrl modular in my design, I add it in the qsys , connect it to two modular by avalon Bus. One is the PCIE , the other is my application modular (APP) . run Qsys to Genarat HDL . a "mm_interconnect_3 " modular will be generated. As below show:
I run the design in my board , PCIE can read and write the DDR4 chip , but my application modular can not read and write the DDR4 chip . single Tap get the "nano_adrv9009_0_m1_waitrequest" keep " high" .
waht is the problem
May I know how do you perform this R/W operation?
I just curious where are all this components come from, is it from Intel IP?
Just for sanity check, is there any connectivity issue between the PCIE modular and APP modular?
Is your design are working as expected in the simulation?
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