DE115 Lab 3 part 2 question Clk does not exist in primitive error

[Altera_Forum]

1. how to fix Clk does not exist in primitive error 

2. when i use NAND(A,B) in DLatch, got error, why can not directly call?  Lab 3  Lab3b.vhd  LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY Lab3b IS PORT (  SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)); END Lab3b;  ARCHITECTURE Structural OF Lab3b IS component DLatch port (Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end component;  BEGIN --process --variable item1 : std_logic := '0'; --variable item2 : std_logic := '0'; --begin --item1 <= SW(0); --item2 <= SW(1); H1:DLatch port map (D => SW(0), Clk => SW(1), Q => LEDR(0)); --end END Structural;  DLatch.vhd  LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY DLatch IS PORT ( Clk, D : IN STD_LOGIC; Q : OUT STD_LOGIC); END DLatch;  ARCHITECTURE Structural OF DLatch IS SIGNAL R_g, S_g, Qa, Qb : STD_LOGIC; ATTRIBUTE keep : boolean; ATTRIBUTE keep of R_g, S_g, Qa, Qb : SIGNAL IS true; BEGIN R_g <= NOT( (NOT D) AND Clk); S_g <= NOT( D AND Clk ); Qa <= NOT (S_g AND Qb); Qb <= NOT (R_g AND Qa);  Q <= Qa; END Structural;

[Altera_Forum]

You need to be more precise about the error messages you get. 

The nand operator exists in VHDL, and you should be able to use it just like and (i.e. "x nand y", not "nand(x,y)" )

[Altera_Forum]

it is the message from studio 

port clk does not exist in primitive DLatch of instance H1 i do not know why got Clk syntax error when connect with SW(1)

[Altera_Forum]

I compiled a project with your two files in Modelsim and it went with no errors, so your problem isn't in the VHDL code. Check that your project is set correctly (i.e. that you are compiling both files, and that they are the right ones). 

I used this scriptvlib work vcom Lab3.vhd vcom DLatch.vhd vsim work.Lab3band got this:Modelsim > do lab3.tcl # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling entity Lab3b # -- Compiling architecture Structural of Lab3b # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling entity DLatch # -- Compiling architecture Structural of DLatch # vsim work.Lab3b # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading work.lab3b(structural) # Loading work.dlatch(structural)

[Altera_Forum]

i rename to DLatch3, success to do D flip flop