DE1SOC max. GPIO Header Frequency

[Altera_Forum]

Hi, 

I have a short question. What is the maximum frequency on the DE1SOC board on the 2 GPIO headers "GPIO 0" and "GPIO 1".  In the user manual I can't find it. I want to merge two FPGAs.  Best regards Michael

[Altera_Forum]

The figure isn't in the manual because the max frequency depends on the rest of the circuit. If you do a proper transmission line design with termination you can get a much higher frequency than by casually connecting the pins together. Distance and the load on the other end also matters.  

 I've been able to get 4 MHZ connecting two FPGA boards together with jumper wires twisted together as a differential pair. It was fast enough for me so I didn't experiment to see how much faster it would go with better termination etc.

[Altera_Forum]

As far as I know, the GPIO frequency is 100 MHz.

[Altera_Forum]

--- Quote Start ---  As far as I know, the GPIO frequency is 100 MHz.  --- Quote End ---    But the maximum Clock Frequency of the FPGA is 50 MHz, or am I wrong?

[Altera_Forum]

There is no guarantee that you can get a 100 Mhz signal out of the FPGA if you don't follow the board layout guidelines. You can't brush this off or disaster awaits. 

 I've worked software on projects that had to be re-done because signals weren't handled correctly. The first design was done by a new grad with no experience. It was annoying because management wanted it fixed in software (impossible) or failing that VHDL (usually impossible). After several wasted months dithering around it was finally decided to give the board design to an engineer who did several high speed boards before and re-spin the board. Most of the problems were fixed the first day the revised board was powered on. The rest were fixed in the next week or so.

[Altera_Forum]

It also depends a lot on the type of I/O you want to drive. The maximum frequency will be lower for 3.3V LVTTL/LVCMOS, for example, compared to SSTL or HSTL signaling. Also depends on whether you employ the on-chip termination (OCT) or not. And how the traces are routed on the PCB (ie, are they routed as 50ohm impedance traces, or just simple non-controlled impedance links).