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VROGE2
New Contributor I
120 Views

DE2-115 Maximum Clock Speed

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I am multiplying the 50MHz clock on a DE2-115 using a Phase Locked Loop. I have been able to multiply the clock and I have verified that it works up to 200MHz. My question is how fast can I get the clock to go before I start to experience errors.

 

Thanks in advance

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Rahul_S_Intel1
Employee
64 Views

Hi ,

 The DE2-115 uses Cyclone IV FPGA , so the PLL frequency depends up on the data sheet specification of Cyclone IV FPGA .

Kindly find the page no: 24 of the below document for the pll specification.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pd...

 

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3 Replies
Rahul_S_Intel1
Employee
64 Views

HI ,

If , I reiterate you question , you need to understand what is the maximum frequency output we can get from the PLL output , if the input frequency is 50Mhz

VROGE2
New Contributor I
64 Views

HI Rahul,

 

I understand that I am able to reach 200MHz because I can see the 200MHz waveform on my Oscilloscope. However, past 200MHz I begin to reach the Bandwidth limit on my oscilloscope so I cannot confirm one way or another if I am actually reaching the speeds at which I am programming the PLL.

 

So my questions are the following:

What is the Maximum Operating Frequency that the DE2-115 can operate at without experiencing errors?

What is the maximum frequency output I can get from the PLL?

 

This is the first time that I am multiplying the clock on an FPGA. I am aware that the FPGA itself is optimized to run at 50MHz but I do not know how far I can push the operating frequency before it starts to behave incorrectly.

Rahul_S_Intel1
Employee
65 Views

Hi ,

 The DE2-115 uses Cyclone IV FPGA , so the PLL frequency depends up on the data sheet specification of Cyclone IV FPGA .

Kindly find the page no: 24 of the below document for the pll specification.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pd...

 

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