DE2-115 PLL dynamic phase doesn't work at low output frequencies?

[Altera_Forum]

We use the ALTPLL MegaWizard Plug-in Manager to build the PLL module. We use this PLL module to generate two same frequency output clock. Then, We use the PLL dynamic phase shifting function to adjust the phase difference between the two output signals.  

 We found the phase shifting between the two output signal works properly for 3MHz and 4MHz. but for lower frequency such as 1mhz and 2mhz, the phase shifting does not work and the phase relation between the two outputs keeps same. The VCO for these outputs are all 1300MHz. I attached the picture of the PLL module below.   Does anyone come to this problem before?   Thanks a lot for your time and consideration!

[Altera_Forum]

It would be interesting to find out if it is the output frequency itself, or the ratio of input/output frequencies. With lower frequencies you may be maxing out the PLL's registers.

[Altera_Forum]

Hi Galfonz, 

 Thank you very much for your reply. It is very much appreciated! I am a very beginner in FPGA.   1. Could you explain more about " if it is the output frequency itself, or the ratio of input/output frequencies." 2. When you say the low frequency might max out the PLL's register, is there anyway to check whether the low frequency max out the register?  Thanks a lot again. Looking forwards to your reply.

[Altera_Forum]

1. To find out if it is the input frequency causing the problem, try it with higher and lower input frequencies but the same desired output frequencies. 

2. Read the PLL section of the Cyclone IV handbook. It should have info about the width in bits of the multiplier and divider registers. The PLL will only generate the correct frequency if the calculated multiplier and divisor will fit into the registers.  Also, look at the calculated phase resolution. You can only request phase differences that are a multiple of this. It may be rounding to zero.